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首页> 外文期刊>Journal of VLSI signal processing systems >Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

机译：基于高级综合的字长感知DSP硬件设计流程

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摘要

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.
机译：诸如视频和图像处理之类的多媒体应用程序通常被视为计算密集型应用程序。对于这些应用程序，数据和指令的字长在整个应用程序中是不同的。生成硬件体系结构并不是一项简单的任务，因为它需要进行深入的字长分析才能正确确定所需的硬件资源。在本文中，我们提出了一种基于高层综合的自动化设计方法，该方法要考虑数据字长和互连资源成本，以便为DSP应用生成面积和功耗高效的定点架构。 ASIC和FPGA技术都是针对性的。实验结果表明，与以前的方法相比，我们提出的方法在FPGA技术上将面积减少了6％至42％，在ASIC上减少了9％至48％。 FPGA技术可节省多达44％的功耗，而ASIC则可节省多达36％的功耗。

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