Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

R. Gutierrez; J. Valls

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Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

机译：使用查找表方法在通信应用中实现atan（Y / X）的低功耗FPGA实现

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This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atari (Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

机译：本文提出了一种计算atan（Y / X）操作的架构，该架构适用于需要20 MHz吞吐量的宽带通信应用。相对于基于CORDIC算法或基于常规LUT的atan（Y / X）运算符，该架构利用了FPGA器件的嵌入式硬核来降低功耗。所提出的架构可以以两个时钟周期的延迟来计算atari（Y / X），其功耗比CORDIC低49％，比多部件方法低46％。

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来源
《Journal of signal processing systems for signal, image, and video technology》 |2009年第1期|25-33|共9页
作者
R. Gutierrez; J. Valls;
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作者单位

Department of Physics and Computer Architecture, Miguel Hernandez University, 03202 Elche, Alicante, Spain;

Department of Electronic Engineering, Polytechnic University of Valencia, 46730 Grao de Gandia, Valencia, Spain;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
atan(Y/X); CORDIC; FPGA; wireless communication;

机译：阿坦（Y / X）;CORDIC;FPGA;无线通信;

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Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

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