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首页> 外文期刊>Journal of Spacecraft Technology >Design of On-Board Controller (OBC-2.3) ASIC based on 180nm CMOS Technology for Synthetic Aperture Radar (SAR)
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Design of On-Board Controller (OBC-2.3) ASIC based on 180nm CMOS Technology for Synthetic Aperture Radar (SAR)

机译：基于180nm CMOS技术的合成孔径雷达（SAR）设计车载控制器（OBC-2.3）ASIC设计

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This paper describes design and development of Radiation Hardened Indigenous On Board Controller (OBC-2.3) Application Specific Integrated Circuit (ASIC), which has been developed for ISRO's various Space-borne Synthetic Aperture Radar (SAR) missions. OBC-2.3 ASIC is used in Transmit/Receive controllers (TRC) to control T/R Modules (TRM) for electronic beam steering. The OBC-2.3 ASIC features an 8-bit micro-controller soft IP core with a 32-bit IEEE 754 compliant Floating Point Co-processor (FPC). The FPC is required for real-time computation of digital phase/attenuation values for TRM from required elevation and azimuth angles. Event Programmable Serial/Parallel Interface (EPSPI) module is needed for Event driven beam configuration data loading to TRMs. Up to 8 TRMs can be simultaneously controlled by a single OBC-2.3 ASIC. Timing Signal Re-generator (TSRG) module contains array of programmable pulse generators. There are total six asynchronous transmitter/receiver (UART) modules for serial communication. This mixed signal ASIC contains RS-422/485 transceiver, ADC, clock oscillator and Linear Voltage Regulator (LVR). The OBC-2.3 ASIC is based on 180nm CMOS process of Semiconductor Laboratory (SCL), India with 256-pin CQFP package. It operates at 24 MHz and dissipates less than 1 Watt. T/R Controller (TRC) sub-system based on this indigenous OBC-2.3 ASIC has been used for ISRO's Radar Imaging Satellites (RISAT-1A/2A/1B).
机译：本文介绍了辐射的设计和开发硬化在船上控制器（OBC-2.3）应用特定集成电路（ASIC）上，已经为ISRO的各种空间合成孔径雷达（SAR）任务开发。 OBC-2.3 ASIC用于发送/接收控制器（TRC）以控制用于电子光束转向的T / R模块（TRM）。 OBC-2.3 ASIC具有8位微控制器软IP核，具有32位IEEE 754兼容浮点协处理器（FPC）。 FPC是来自所需高度和方位角的TRM的数字相位/衰减值的实时计算。事件可编程串行/并行接口（EPSPI）模块需要对TRMS进行事件驱动的光束配置数据加载。最多8个TRMS可以通过单个OBC-2.3 ASIC同时控制。定时信号重新发生器（TSRG）模块包含可编程脉冲发生器阵列。有六个异步发射器/接收器（UART）模块用于串行通信。这种混合信号ASIC包含RS-422/485收发器，ADC，时钟振荡器和线性稳压器（LVR）。 OBC-2.3 ASIC基于180nm CMOS的半导体实验室（SCL），印度，带256针CQFP封装。它以24 MHz运行，并耗散不到1瓦特。 T / R控制器（TRC）基于该土着OBC-2.3 ASIC的子系统已被用于ISRO的雷达成像卫星（Risat-1a / 2a / 1b）。

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