Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications’ needs through hardware reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal cluster size of the architecture.
展开▼
