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首页> 外文期刊>The Journal of Systems and Software >Logic synthesis for PAL-based CPLD-s based on two-stage decomposition
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Logic synthesis for PAL-based CPLD-s based on two-stage decomposition

机译：基于两阶段分解的基于PAL的CPLD的逻辑综合

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摘要

A PAL-based (PAL - Programmable Array Logic) logic block is the core of a great majority of contemporary CPLD (Complex Programmable Logic Device) circuits. The purpose of the paper is to present a novel method of two-stage decomposition dedicated for PAL-based CPLD-s. The key point of the algorithm lies in sequential search for a decomposition providing feasibility of implementation of the free block in one PAL-based logic block containing a limited number of product terms. The proposed method is an alternative to the classical approach, based on two-level minimisation of separate single-output functions. An original method of determining the row multiplicity of the partition matrix is presented. For this purpose a new concept of graph is proposed - the Row Incompatibility and Complement Graph. An appropriate algorithm of the Row Incompatibility and Complement Graph colouring is presented. On the basis of row multiplicity evaluated for individual partitionings, the partitioning which provides minimisation of the bound block is chosen. Results of the experiments, which are also presented, prove that the proposed method leads to significant reduction of chip area in relation to the classical approach, especially for CPLD structures, that consist of PAL-based blocks containing 2~i (a power of 2) product terms. The proposed method was also compared with decomposition algorithms presented in another works. The results lead to a conclusion, that the proposed two-stage PAL decomposition is especially attractive with respect to the number of logic levels obtained.
机译：基于PAL的（PAL-可编程阵列逻辑）逻辑模块是当今大多数CPLD（复杂可编程逻辑器件）电路的核心。本文的目的是提出一种专用于基于PAL的CPLD-s的新型两阶段分解方法。该算法的关键在于顺序搜索分解，从而为在包含有限数量乘积项的基于PAL的逻辑块中实现自由块提供了可行性。所提出的方法是基于单独的单个输出函数的两级最小化的经典方法的替代方法。提出了确定分区矩阵的行多重性的原始方法。为此，提出了一种新的图形概念-行不兼容和补图。提出了行不兼容和补图着色的适当算法。基于为单个分区评估的行多重性，选择提供绑定块最小化的分区。还给出了实验结果，证明与传统方法相比，该方法可显着减少芯片面积，尤其是对于CPLD结构而言，该结构由包含2〜i（2的幂）的基于PAL的块组成）产品条款。还将该提议的方法与另一篇著作中提出的分解算法进行了比较。结果得出结论，就获得的逻辑电平数量而言，拟议的两级PAL分解特别具有吸引力。

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