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Theoretical study of charge trapping levels in silicon nitride using the LDA-1/2 self-energy correction scheme for excited states

机译：使用LDA-1 / 2自能量校正方案对激发态进行氮化硅中电荷陷阱能级的理论研究

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Silicon nitride, with a permittivity mid-way between SiO_2 and common high-k materials such as HfO_2, is widely used in microelectronics as an insulating layer on top of oxides where it serves as an impurity barrier with the positive side effect of increasing the dielectric constant of the insulator when it is SiC>2. It is also employed as charge storage in nonvolatile memory devices thanks to its high concentration of charge traps. However, in the case of memories, it is still unclear which defects are responsible for charge trapping and what is the impact of defect concentration on the structural and electronic properties of SiN_x. Indeed, for the amorphous phase the band gap was measured in the range 5.1-5.5 eV, with long tails in the density of states penetrating the gap region. It is still not clear which defects are responsible for the tails. On the other hand, the K-center defects have been associated with charge trapping, though its origin is assigned to one Si back bond. To investigate the contribution of defect states to the band edge tails and band gap states, we adopted the β phase of stoichiometric silicon nitride (P-Si_3N_4) as our model material and calculated its electronic properties employingab initio DFT/LDA simulations with self-energy correction to improve the location of defect states in the SiN_x band gap through the correction of the band gap underestimation typical of DFT/LDA. We considered some important defects in SiN_x, as the Si anti-site and the N vacancy with H saturation, in two defect concentrations. The location of our calculated defect levels in the band gap correlates well with the available experimental data, offering a structural explanation to the measured band edge tails and charge trapping characteristics.
机译：氮化硅的介电常数介于SiO_2和常见的高k材料（例如HfO_2）之间，在微电子学中被广泛用作氧化物顶部的绝缘层，在该层中，它用作杂质阻挡层，具有增加电介质的积极副作用当SiC> 2时，绝缘子的常数。由于电荷陷阱的高度集中，它也被用作非易失性存储设备中的电荷存储。然而，在存储器的情况下，仍不清楚哪些缺陷导致电荷俘获，以及缺陷浓度对SiN_x的结构和电子性能的影响是什么。实际上，对于非晶相，带隙的测量范围为5.1-5.5 eV，状态密度的长尾巴穿过间​​隙区域。尚不清楚哪些缺陷是造成尾部的原因。另一方面，尽管K中心缺陷的起源被分配给一个Si背键，但其与电荷俘获有关。为了研究缺陷态对带边缘尾部和带隙态的贡献，我们采用化学计量的氮化硅（P-Si_3N_4）的β相作为模型材料，并使用自能从头算DFT / LDA模拟来计算其电子性能。通过校正DFT / LDA典型的带隙低估来校正SiN_x带隙中缺陷状态的位置。我们在两个缺陷浓度中考虑了SiN_x中的一些重要缺陷，例如Si反位和具有H饱和的N空位。我们计算出的缺陷能级在带隙中的位置与可用的实验数据很好地相关，从而对测得的带边缘尾部和电荷俘获特性提供了结构上的解释。

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