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An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

机译：基于梯形图的VHDL布尔表达式生成算法

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摘要

This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-) based programmable logic controllers (PLCs), where an effective conversion from an LD to its associated Boolean expressions seems rarely mentioned. Based on this core thought, the conversion process of the algorithm first involves abstracting and expressing the encountered LD as an activity-on-vertex (AOV) graph. Next, an AND-OR tree in which AND-nodes and OR-nodes connote the series and the parallel relationships between the vertices of the AOV graph is constructed based on the AOV graph. Therefore, by a traversal to the AND-OR tree, the associated Boolean expression, as the output of the algorithm, can be easily obtained in VHDL. The proposed algorithm is then verified with an illustrative example, wherein a complicated LD is given as the input.
机译：这项研究提出了一种在梯形图（LD）作为输入的情况下在VHDL中生成关联布尔表达式的算法。该算法的目的是实现基于现场可编程门阵列（FPGA）的可编程逻辑控制器（PLC），在这种情况下，从LD到其关联的布尔表达式的有效转换似乎很少被提及。基于此核心思想，算法的转换过程首先涉及将遇到的LD抽象并表示为顶点活动（AOV）图。接下来，基于AOV图构造AND-OR树，在该AND-OR树中，AND节点和OR节点表示序列，并且AOV图的顶点之间的平行关系。因此，通过遍历AND-OR树，可以在VHDL中轻松获得相关的布尔表达式作为算法的输出。然后用说明性示例验证提出的算法，其中以复杂的LD作为输入。

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  • 来源
    《Mathematical Problems in Engineering》 |2015年第2期|530586.1-530586.10|共10页
  • 作者

    Xie Hongxia; Zhuang Zheng-Yun;

  • 作者单位

    Zhejiang Univ, City Coll, Sch Comp & Comp Sci, Hangzhou 310015, Zhejiang, Peoples R China.;

    Zhejiang Univ, City Coll, Sch Comp & Comp Sci, Hangzhou 310015, Zhejiang, Peoples R China.;

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