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High Real-Time Design of Digital Pulse Compression Based on FPGA

机译:基于FPGA的数字脉冲压缩的高实时性设计

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摘要

Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. Theproposed method adopts "pipeline and parallel" structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.
机译:由于就地快速傅立叶变换的实时性较差,因此研究并设计了一种基于实时抽取和单浮点计算的可重配置基4 FFT处理器。提出的方法采用“流水线并行”结构访问多个存储器,以提高FFT处理速度,然后应用于数字脉冲压缩。实验结果表明,所提出的基于基数4的FFT无需增加硬件资源即可快速实现数字脉冲压缩。所提出的方法也可以应用于其他基数FFT。

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  • 来源
    《Mathematical Problems in Engineering》 |2015年第5期|792862.1-792862.7|共7页
  • 作者单位

    Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China.;

    Chinese Acad Sci, Inst Elect, Beijing 100190, Peoples R China.;

    Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China.;

    Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China.;

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