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首页> 外文期刊>Mathematical Problems in Engineering >Designing All-Pole Filters for High-Frequency Phase-Locked Loops
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Designing All-Pole Filters for High-Frequency Phase-Locked Loops

机译：设计用于高频锁相环的全极点滤波器

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摘要

Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise frequency and phase references are required. Among these applications, synchronous telecommunication networks experienced a strong development in order to support the explosive information traffic that the modern society demands. Consequently, bandwidth became a decisive parameter, implying higher and higher frequencies for the clock signals exchanged between the nodes of the networks and detected by PLLs. The necessity to improve clock precision that follows the bandwidth increase provoked the improvement of the filter component of the PLLs, avoiding instability and high-frequency components in the reference signals. Here, a technique of designing this kind of filter is presented, considering second-order filters, implying third-order PLLs. Simulations show that following this technique produces very fast tracking processes, enabling precise operation even for very high frequencies.
机译：由于锁相环（PLL）电路是在1930年代提出的，因此它被用于许多需要精确的频率和相位参考的情况。在这些应用中，同步电信网络经历了强大的发展，以支持现代社会所需的爆炸性信息通信。因此，带宽成为决定性的参数，这意味着在网络节点之间交换并由PLL检测到的时钟信号的频率越来越高。随着带宽的增加，必须提高时钟精度，这导致了PLL滤波器成分的改善，避免了参考信号中的不稳定和高频成分。在此，介绍了一种设计这种滤波器的技术，其中考虑了二阶滤波器，这意味着三阶PLL。仿真表明，采用这种技术会产生非常快速的跟踪过程，即使在非常高的频率下也能实现精确的操作。

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