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首页> 外文期刊>The mediterranean journal of electronics and communications >DESIGN OF HIGH PERFORMANCE CARRY ADDERS USING REVERSIBLE LOGIC
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DESIGN OF HIGH PERFORMANCE CARRY ADDERS USING REVERSIBLE LOGIC

机译：基于可逆逻辑的高性能随身广告设计

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Reversible logic is gaining importance in the context of upcoming fields such as nanotechnology, cellular automata, quantum level computation and low power VLSI design. There is one to one correspondence between input and output vectors; hence these circuits do not lose any information during computation. In this work we have implemented novel 4-bit binary adders using reversible logic. All the proposed circuits have been designed at 90nm CMOS technology using Cadence Virtuoso software. Based on the results of the proposed adders, we conclude that carry look ahead (CLA) adder gives best performance. As compared to its conventional version, the requirement of number of gates is reduced by almost 60%, ancillary inputs have reduced by 46% and number of garbage outputs have reduced by almost 48%. The proposed CLA adder may also find application in multiply and accumulate units.
机译：在诸如纳米技术，细胞自动机，量子能级计算和低功耗VLSI设计等即将出现的领域中，可逆逻辑变得越来越重要。输入向量和输出向量之间存在一对一的对应关系；因此，这些电路在计算过程中不会丢失任何信息。在这项工作中，我们使用可逆逻辑实现了新颖的4位二进制加法器。所有提议的电路均已使用Cadence Virtuoso软件在90nm CMOS技术下进行设计。根据提议的加法器的结果，我们得出结论，进位超前（CLA）加法器可提供最佳性能。与传统版本相比，门数量减少了近60％，辅助投入减少了46％，垃圾产出减少了近48％。提出的CLA加法器也可以在乘法和累加单元中找到应用。

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