首页> 外文期刊>The mediterranean journal of electronics and communications >RESISTORLESS 45nm SWITCHED INVERTER SCHEME ANALOG TO DIGITAL CONVERTER FOR LOW POWER AND HIGH SPEED APPLICATIONS
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RESISTORLESS 45nm SWITCHED INVERTER SCHEME ANALOG TO DIGITAL CONVERTER FOR LOW POWER AND HIGH SPEED APPLICATIONS

机译:适用于低功率和高速应用的电阻式45nm开关反相器方案模拟数字转换器

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The Analog to Digital converters play a very important role in today's world of electronics. Out of the various types of ADCs available the flash ADC is most popular for its highest conversion rate and its wide applications. But it dissipates high power due to the presence of resistance ladder. In this research two different approaches are presented which eliminates the resistor ladder completely and hence reduce the power demand drastically. The first approach is Switched Inverter Scheme (SIS) ADC; it is realized for 3 bits using 7 comparator circuits of varying size in CMOS 45nm technology with Predictive Technology Model (PTM). The test result obtained indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts; Power delay product (PDP) is 415.9 fWs, and the area overhead is 1.89μm2. The second approach is Sleep transistor SIS ADC. This approach shows 71% improvement in power dissipation. Whereas PDP is found to be 107.3 fWs and area overhead is 1.94 μm2 for Sleep transistor SIS ADC.
机译:模数转换器在当今的电子世界中扮演着非常重要的角色。在各种可用的ADC中,闪存ADC以其最高的转换率和广泛的应用而最受欢迎。但是由于存在电阻阶梯,它会消耗高功率。在这项研究中,提出了两种不同的方法,它们完全消除了梯形电阻,从而大大降低了功率需求。第一种方法是开关逆变器方案(SIS)ADC。它使用具有预测技术模型(PTM)的CMOS 45nm技术中的7个大小不同的比较器电路实现3位。获得的测试结果表明偏移误差为0.014 LSB。满量程误差为-0.112LSB。增益误差为0.07 LSB,实际满量程范围为0.49V,最坏情况下的DNL和INL均为-0.3V。 SIS ADC的功耗为207.987微瓦;功率延迟积(PDP)为415.9 fWs,面积开销为1.89μm2。第二种方法是休眠晶体管SIS ADC。这种方法的功耗降低了71%。睡眠晶体管SIS ADC的PDP为107.3 fWs,面积开销为1.94μm2。

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