Peeling model of dielectric film including low-k material on wafer edge

Nobuyoshi Sato

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Peeling model of dielectric film including low-k material on wafer edge

机译：晶圆边缘包含低k材料的介电膜剥离模型

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This study explores and clarifies a peeling model of multilayered films caused by a stacked low dielectric constant (low-k) material on a wafer edge. The dielectric is deposited by chemical vapor deposition (CVD) and composed of a low-k film (methyl-doped silicon oxide) embedded between plasma-enhanced CVD (PE-CVD) SiO_2 layers, which consist of a cap (upper) and base (bottom) layer. We found that peeling occurs from the cap layer during thermal treatment and is accelerated when core particles (CP) are present under the base layer at the wafer edges. In addition, the peeling increased as the low-k film thickness increased. However, the peeling decreased after plasma treatment. Based on these findings, we propose a possible model of peeling.

机译：这项研究探索并阐明了由晶片边缘上堆叠的低介电常数（low-k）材料引起的多层膜剥离模型。电介质通过化学气相沉积（CVD）进行沉积，并由嵌入在等离子增强CVD（PE-CVD）SiO_2层之间的低k膜（甲基掺杂的氧化硅）组成，该层由盖（上层）和基底组成（底层。我们发现，在热处理期间会从覆盖层发生剥离，并且当核心颗粒（CP）存在于晶圆边缘的基础层下方时，剥离会加速。另外，随着低k膜厚度的增加，剥离增加。但是，等离子处理后的剥离减少。基于这些发现，我们提出了一种可能的脱皮模型。

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来源
《Microelectronic Engineering》 |2014年第10期|31-35|共5页
作者
Nobuyoshi Sato;
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作者单位

Advanced Memory Development Center, Toshiba Corporation, Yokkaichi-Shi, Mie Prefecture 512-8550, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
原文格式 PDF
正文语种 eng
中图分类
关键词
Peeling; Low-k material; Wafer edge;

机译：脱皮;低介电常数材料晶圆边缘;

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Peeling model of dielectric film including low-k material on wafer edge

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