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Improving the subthreshold performance of junctionless transistor using spacer engineering

机译：使用间隔工程提高无结晶体管的亚阈值性能

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摘要

In this brief, an attempt has been made to improve the ultra-low power (ULP) performance of junctionless transistor (JLT) using spacer engineering. The length of gate sidewall dual-k (high-k and low-k) spacers are optimized to improve the ULP performance of JLT. Proposed device (Dual-k JLT) shows improvement in on current (I-on) by 72.5%, drain induced barrier lowering (DIBL) by 37.8%, subthreshold swing (SS) by 6.5%, and intrinsic delay by 35.4% at supply voltage (V-DD) of 0.4 V and matched off -state current (I-off) of 10-(11) A/mu m in comparison to the conventional JLT. Moreover, Dual-k JLT devices show competitive ULP performance in comparison to the inversion mode (IM) underlap device. Effect of V-DD scaling on ULP performance of the JLT devices has also been studied. The effect of dual-k spacer on Junctionless accumulation-mode (JAM) device is also studied and found superior values of all the performance metrics compared to Dual-k JLT and IM devices.
机译：在本简介中，已尝试使用间隔工程来改善无结晶体管（JLT）的超低功耗（ULP）性能。优化栅极侧壁双k（高k和低k）间隔物的长度，以提高JLT的ULP性能。拟议的器件（Dual-k JLT）的导通电流（I-on）提高了72.5％，漏极引起的势垒降低（DIBL）降低了37.8％，亚阈值摆幅（SS）降低了6.5％，供电时的固有延迟降低了35.4％与传统的JLT相比，它的电压（V-DD）为0.4 V，匹配的断态电流（I-off）为10-（11）A /μm。此外，与反相模式（IM）重叠式器件相比，双k JLT器件还具有极好的ULP性能。还研究了V-DD缩放对JLT设备的ULP性能的影响。还研究了双k隔离层对无结累积模式（JAM）器件的影响，发现与Dual-k JLT和IM器件相比，所有性能指标的值都较高。

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  • 来源
    《Microelectronics journal》 |2017年第1期|55-58|共4页
  • 作者

    Saini Gaurav; Choudhary Sudhanshu;

  • 作者单位

    Natl Inst Technol, Dept Elect & Commun Engn, Kurukshetra 136119, Haryana, India|Natl Inst Technol, Sch VLSI Design & Embedded Syst, Kurukshetra 136119, Haryana, India;

    Natl Inst Technol, Dept Elect & Commun Engn, Kurukshetra 136119, Haryana, India|Natl Inst Technol, Sch VLSI Design & Embedded Syst, Kurukshetra 136119, Haryana, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Dual-k spacer; Intrinsic delay; JLT; SCEs;

    机译：Dual-k spacer;固有延迟;JLT;SCEs;

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