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首页> 外文期刊>Microelectronics journal >Parallel SER analysis for combinational and sequential standard cell circuits
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Parallel SER analysis for combinational and sequential standard cell circuits

机译：组合和顺序标准单元电路的并行SER分析

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A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits. ASSET-VLG was constructed in practically oriented way: (i) it employs a verilog parser for automatically reading the synthesized DUT (device under test) netlist; (ii) it provides an accurate and unified SER analysis framework for both the combinational and sequential circuits rather than the former only; (iii) it targets to a 130 nm production library and the modeling method can be easily ported to newer technologies. Furthermore, concurrency is also exploited for accelerating the evaluation procedure on modern multi -core computers. These features make ASSET-VLG appropriate for automatic SER estimation in design stage and can be easily integrated into current highly reliable ICs design flow. Experiments on ISCAS'85 and ISCAS'89 benchmark circuits show the evaluation time ranges from 0.5 ms to 2.16 s without previous memory explosion problem. Compared with spice, the modeling method of ASSET-VLG provides 98% accuracy. The parallelizing experiments indicate the proposed method has better scalability, e.g., 4.44 X speedup are obtained in a 4 cores/8 threads platform. The experiments also reveal that sequential part (flip-flops) in the circuit dominating the system SER by one order than combinational gates for a 130 nm CMOS process. Last but not least, significant frequency dependence of SER are observed in flip-flops, implying the commonly used critical charge measure is insufficient for characterizing soft error in sequential cells. (C) 2016 Elsevier Ltd. All rights reserved.
机译：开发了并行SER（软错误率）评估框架ASSET-VLG，以分析组合和顺序标准单元电路的SER。 ASSET-VLG以实用的方式构建：（i）它使用Verilog解析器自动读取合成的DUT（被测设备）网表； （ii）它为组合电路和顺序电路提供了准确而统一的SER分析框架，而不仅仅是前者； （iii）它以130 nm生产库为目标，并且建模方法可以轻松移植到新技术上。此外，并发还被用于加速现代多核计算机上的评估过程。这些功能使ASSET-VLG适合在设计阶段进行自动SER估算，并且可以轻松集成到当前高度可靠的IC设计流程中。在ISCAS'85和ISCAS'89基准电路上进行的实验表明，评估时间范围为0.5 ms至2.16 s，没有先前的内存爆炸问题。与香料相比，ASSET-VLG的建模方法可提供98％的准确性。并行化实验表明，该方法具有更好的可扩展性，例如，在4核/ 8线程平台上可获得4.44 X加速。实验还表明，在130 nm CMOS工艺中，电路中的顺序部分（触发器）比组合门控制系统SER高一阶。最后但并非最不重要的是，在触发器中观察到SER的明显频率依赖性，这意味着常用的临界电荷测量不足以表征连续单元中的软错误。 （C）2016 Elsevier Ltd.保留所有权利。

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