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首页> 外文期刊>Microelectronics journal >A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability
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A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

机译：具有超高输出电流驱动能力的新型低压超低功耗CMOS AB类电流输出级

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In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate-source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μrn CMOS technology parameters. Under supply voltage of ± 0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than -53 dB and extremely high output impedance of 320 MO while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_(outmax)/I_(bias) or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ± 0.9 V, it can deliver extremely large output current of ± 24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than -45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ± 3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR-) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.
机译：本文提出了一种具有极高线性度和高输出阻抗的新型低压（LV）超低功耗（VLP）AB类电流输出级（COS）。一种新颖的电流分配方法用于最小化提供LV操作和超高电流驱动能力的晶体管栅极-源极电压。采用新颖的基于电阻器的电流镜可实现高线性度和非常高的输出阻抗，从而避免使用传统的共源共栅结构。建议的COS的运行已通过基于TSMC 0.18μmCMOS技术参数的HSPICE仿真进行了验证。在±0.7 V的电源电压和5μA的偏置电流下，它可以提供高达14 mA的输出电流，THD优于-53 dB，并且输出阻抗高达320 MO，而功耗仅为29μW。这使得拟议的COS具有2800的超大电流驱动比（I_（outmax）/ I_（bias）或峰值输出电流与输出分支晶体管的偏置电流之比）。通过将电源电压提高到±0.9 V，它可以提供±24 mA的超大输出电流，对应于3200电流驱动比，而仅消耗42.9μW，并具有350MΩ的高输出阻抗。有趣的是，拟议的COS是第一个报告的，具有如此高的输出电流和THD甚至小于-45 dB。这种超高电流驱动能力，高线性度和高输出阻抗使所提出的COS成为LV，VLP和高驱动电流模式电路的绝佳选择。通过在这项工作中证明常规COS在相同条件下只能提供±3.29 mA的电流，所提出的COS的优越性变得更加重要。拟议的COS还具有分别为125 dB和130 dB的高正电源抑制比和负电源抑制比（PSRR + / PSRR-）。这使其非常适合LV，VLP混合模式应用。提供了蒙特卡洛模拟结果，证明了所提出的模块相对于过程公差的出色鲁棒性能。有利地，所提出的COS解决了电流输出级的主要限制，迄今为止，该主要输出限制已阻止了在低电源电压下设计高驱动电流模式电路。简而言之，如此众多有效的新颖方法的有意结合，对科学和工程界提出了一个奇妙的COS障碍。

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