AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology

Locati J.; Della Marca V.; Rivero C.; Fornara P.; Regnier A.; Niel S.; Coulie K.

首页> 外文期刊>Microelectronics & Reliability >AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology

【24h】

AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology

机译：非易失性存储器技术新型垂直MOS晶体管的交流应力可靠性研究

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in an NVM environment. Finally, the AC stress reliability results demonstrate significant instabilities of both parasitic and main transistors. The comprehension is supported by TCAD simulations.

机译：本文介绍了一种新型高压垂直沟槽MOS晶体管，设计用于非易失性存储器（NVM）技术。证明了在AC应激期间观察到的一些现象的巨大驼峰效应。还示出了准静态测量结果表明，该垂直沟槽MOS晶体管可以适用于NVM环境中的使用。最后，交流应力可靠性结果表明了寄生和主晶体管的显着不稳定性。 TCAD模拟支持理解。

著录项

来源
《Microelectronics & Reliability》 |2020年第11期|113810.1-113810.7|共7页
作者
Locati J.; Della Marca V.; Rivero C.; Fornara P.; Regnier A.; Niel S.; Coulie K.;
展开▼
作者单位

STMicroelectronics 190 Ave Celestin Coq F-13106 Rousset France|Aix Marseille Univ CNRS UMR 7334 F IM2NP F-13997 Marseille France;

Aix Marseille Univ CNRS UMR 7334 F IM2NP F-13997 Marseille France;

STMicroelectronics 190 Ave Celestin Coq F-13106 Rousset France;

STMicroelectronics 190 Ave Celestin Coq F-13106 Rousset France;

STMicroelectronics 190 Ave Celestin Coq F-13106 Rousset France;

STMicroelectronics 190 Ave Celestin Coq F-13106 Rousset France;

Aix Marseille Univ CNRS UMR 7334 F IM2NP F-13997 Marseille France;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词

相似文献

外文文献
中文文献
专利

1. Non-Volatile Organic Memory Elements Based on Carbon-Nanotube-Enabled Vertical Field-Effect Transistors [J] . Bo Liu, Mitchell A. McCarthy, Andrew C. Rinzler Advanced Materials for Optics and Electronics . 2010,第20期

机译：基于碳纳米管的垂直场效应晶体管的非易失性有机存储元件
2. Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods [J] . Quentin Rafhay, M. Florian Beug, Russell Duane Solid-State Electronics . 2007,第4期

机译：浮栅非易失性存储器中栅极电容耦合系数的提取：虚拟单元提取方法中浮栅存储器与参考晶体管失配影响的统计研究
3. Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- k -Metal-Gate CMOS Technologies [J] . Faraz Khan, Eduard Cartier, Jason C. S. Woo, Electron Device Letters, IEEE . 2017,第1期

机译：电荷陷阱晶体管（CTT）：嵌入式逻辑兼容的多次可编程的非易失性存储元件，用于高k金属门CMOS技术
4. AC stress reliability study of a new high voltage transistor for logic memory circuits [C] . J. Locati, V. Della-Marca, C. Rivero, International Reliability Physics Symposium . 2020

机译：用于逻辑存储电路的新型高压晶体管的交流应力可靠性研究
5. Charge Trap Transistors (CTT): Turning Logic Transistors into Embedded Non-Volatile Memory for Advanced High-k/Metal Gate CMOS Technologies [D] . Khan, Faraz. 2020

机译：电荷陷阱晶体管（CTT）：将逻辑晶体管转换为高级高k /金属门CMOS技术的嵌入式非易失性存储器
6. Non-Volatile Transistor Memory with a Polypeptide Dielectric [O] . Lijuan Liang, Wenjuan He, Rong Cao, 2020

机译：多肽电介质的非易失性晶体管存储器
7. Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies [O] . Faraz Khan, Eduard Cartier, Jason C. S. Woo, 2017

机译：电荷陷阱晶体管（CTT）：嵌入式完全逻辑兼容的多时可编程非易失性的非易失性存储器，用于高-$ k $-$-$-Metal-Gate CMOS技术

AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology

摘要

著录项

相似文献

相关主题

期刊订阅