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Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

机译：高速I / O应用中ESD保护二极管的固有特性研究

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摘要

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R_(ON)* C_(ESD), I_(CP)/C_(ESD). V_(HBM)/C_(ESD), and I_(CP)/A_(Layout)) of ESD protection diodes with new proposed layout styles can be successfully improved.
机译：为了满足所需的静电放电（ESD）坚固性，将ESD二极管添加到集成电路（IC）的I / O单元中。但是，ESD二极管产生的寄生电容通常会导致电路性能下降，尤其是在高速I / O应用中。在这项工作中，提出了两种改进的布局样式以有效提高ESD保护二极管的品质因数（FOM），它们被称为多格子和多格子空心布局样式。在90纳米CMOS工艺中的实验结果已确认FOM（R_（ON）* C_（ESD），I_（CP）/ C_（ESD），V_（HBM）/ C_（ESD）和I_（CP）可以成功改善具有新提议的布局样式的ESD保护二极管的/ A_（Layout））。

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  • 来源
    《Microelectronics reliability》 |2012年第6期|p.1020-1030|共11页
  • 作者

    Chih-Ting Yeh; Ming-Dou Ker;

  • 作者单位

    Testing Engineering Department, Design Automation Technology Division, Information and Communications Research Laboratories, Industrial Technology Research Institute,Chutung, Hsinchu, Taiwan,Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan;

    Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan,Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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