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Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

机译：建模和仿真支持的ESD保护设备的可靠性分析和优化

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摘要

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC's is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.
机译：提出了一种由先进的二维混合模式电热器件支持的静电放电（ESD）保护结构的分析，并使用经过校准的电物理模型进行电路仿真，以提高受保护IC的可靠性。定义并通过实验验证了临界温度作为破坏设备的标准。在非常短的ESD脉冲期间，对被分析结构的内部电物理特性进行数值模拟和可视化，可以大大改善对它们物理行为的理解，并有助于对被分析ESD保护器件的掺杂和几何形状进行适当的设计和优化。被分析的设备被设计为具有非常高的鲁棒性，可以抵御人体模型（HBM）和国际机电委员会模型（IEC）61000-4-2。所获得的结果显示在两个实例上。第一示例的主题是通过将ESD二极管的阴极触点分为两部分来实现对器件布局的修改，从而减小了具有改善的电特性的面积。第二示例中介绍了掺杂波动对器件鲁棒性的影响。介绍了HBM和IEC脉冲期间二极管和晶体管结构的不同触发和故障机制。

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  • 来源
    《Microelectronics reliability》 |2012年第6期|p.1031-1038|共8页
  • 作者

    A. Chvala; D. Donoval; P. Beno; J. Marek; P. Pribytny; M. Molnar;

  • 作者单位

    Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava 4, Slovak Republic;

    Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava 4, Slovak Republic;

    Bratislava Development Center, ON Semiconductor, Tower 115, Pribinova 25, 810 11 Bratislava, Slovak Republic;

    Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava 4, Slovak Republic;

    Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava 4, Slovak Republic;

    Slovak University of Technology in Bratislava, Ilkovicova 3, 812 19 Bratislava 4, Slovak Republic;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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