Low cost and highly reliable hardened latch design for nanoscale CMOS technology

Haiqing Nan; Ken Choi

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Low cost and highly reliable hardened latch design for nanoscale CMOS technology

机译：低成本和高度可靠的硬化锁存器设计，用于纳米级CMOS技术

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With technology node shrinking, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for soft error caused by high energy particles and not all the nodes are under soft error protection. Therefore, in this paper we propose a low cost hardened latch design in 45 nm CMOS technology with full protection for all internal nodes as well as output node against soft error. Moreover, the proposed hardened approach is technology independent. Compared to previous hardened latch designs, the proposed design reduces cost in terms of power delay product (PDP) 59% on average.

机译：随着技术节点的缩小，单个芯片对软错误的敏感性增加。因此，电路的临界电荷（Qcrit）降低，并且随着技术的进一步发展，这种降低有望继续。在本文中，对先前的强化锁存电路进行了分析，发现先前的设计对软错误的保护有限，特别是对于由高能粒子引起的软错误，并且并非所有节点都处于软错误保护之下。因此，在本文中，我们提出了一种采用45 nm CMOS技术的低成本强化锁存器设计，可以针对所有内部节点以及输出节点提供针对软错误的全面保护。此外，建议的强化方法与技术无关。与以前的强化锁存器设计相比，该建议的设计将功率延迟乘积（PDP）平均降低了59％。

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来源
《Microelectronics reliability》 |2012年第6期|p.1209-1214|共6页
作者
Haiqing Nan; Ken Choi;
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作者单位

Department of Electrical and Computer Engineering, Illinois Institute of Technology. Chicago, IL 60616, United States;

Department of Electrical and Computer Engineering, Illinois Institute of Technology. Chicago, IL 60616, United States;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
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Low cost and highly reliable hardened latch design for nanoscale CMOS technology

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