• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Microelectronics & Reliability >Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors
【24h】

Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors

机译：界面电荷对直流偏置应力引起的非晶氧化物薄膜晶体管变形和传输特性偏移的影响

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The presence of a deformation or hump in the subthreshold region of the transfer characteristic of Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) has been observed after DC stress and related to different causes. In previous works, it has been shown that in devices with active-layer thickness greater than 120 nm, a region with relatively high conductivity remains near the back interface of the active layer, providing a parallel current path between drain and source giving rise to this deformation. If this is the cause of the hump, it should be present independently of bias stress. However, experiments show that the hump is observed in AOS TFTs with active layer thickness below 120 nm and only after DC stress. In this work we show that, if during DC bias stress, the density of positively charged states at the interface between the active layer and the passivation layer of an AOS TFT becomes high enough to provide a parallel conduction path, the deformation or hump in the transfer curve can appear. This condition is more likely to occur in devices passivated with dielectrics that can present charged traps at the dielectric-semiconductor interface and agrees well with experimental data reported for AOS TFTs.
机译：在直流应力作用下，已经观察到非晶氧化物半导体（AOS）薄膜晶体管（TFT）的传输特性的亚阈值区域中存在变形或驼峰，并且其原因不同。在以前的工作中，已经表明，在有源层厚度大于120 nm的器件中，具有相对较高电导率的区域保留在有源层的背面附近，从而在漏极和源极之间提供了平行的电流路径，从而导致了这种情况。形变。如果这是导致驼峰的原因，则应独立于偏压力而出现。然而，实验表明，在有源层厚度低于120 nm的AOS TFT中，仅在直流应力之后才观察到驼峰。在这项工作中，我们表明，如果在直流偏置应力期间，AOS TFT的有源层和钝化层之间的界面处带正电的状态的密度变得足够高，以提供平行的导电路径，则在AOS TFT中会产生变形或驼峰。传输曲线会出现。这种情况更可能发生在被电介质钝化的器件中，该器件会在电介质-半导体界面处出现电荷陷阱，并且与AOS TFT的实验数据非常吻合。

著录项

  • 来源
    《Microelectronics & Reliability》 |2012年第7期|p.1342-1345|共4页
  • 作者

    Magali Estrada; Antonio Cerdeira; Benjamin Iniguez;

  • 作者单位

    Seccion de Electronica del Estado Sotido, Depto. Ingenierta Electrica, CINVESTAV-IPN, Av. IPN 2508, Apto. Postal 14-740, 07360 Mexico D.F., Mexico;

    Seccion de Electronica del Estado Sotido, Depto. Ingenierta Electrica, CINVESTAV-IPN, Av. IPN 2508, Apto. Postal 14-740, 07360 Mexico D.F., Mexico;

    Departament dEnginyeria Elearonica Electrica i Automatica, Universitat Rovira i Virgili, Avda. Paisos Catalans 26, 43007 Tarragona, Spain;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号