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Leakage aware resource management approach with machine learning optimization framework for partially reconfigurable architectures

机译：带有机器学习优化框架的泄漏感知资源管理方法，用于部分可重配置的体系结构

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Shrinking size of transistors has enabled us to integrate more and more logic elements into FPGA chips leading to higher computing power. However, it also brings a serious concern to the leakage power dissipation of the FPGA devices. One of the major reasons for leakage power dissipation in FPGA is the utilization of prefetching technique to minimize the reconfiguration overhead (delay) in Partially Reconfigurable (PR) FPGAs. This technique creates delays between the reconfiguration and execution parts of a task, which may lead up to 38% leakage power of FPGA since the SRAM-cells containing reconfiguration information cannot be powered down. In this work, a resource management approach (RMA) containing scheduling, placement and post-placement stages has been proposed to address the aforementioned issue. In scheduling stage, a leakage-aware priority function is derived to cope with the leakage power. The placement stage uses a cost function that allows designers to determine the desired trade-off between performance and leakage-saving. The post-placement stage employs a heuristic approach to close the gaps between reconfiguration and execution of tasks, hence further reduce leakage waste. To further examine the trade-off between performance (schedule length) and leakage waste, we propose a framework to utilize the Genetic Algorithm (GA) for exploring the design space and obtaining Pareto optimal design points. Addressing the time-consuming limitation of GA, we apply Regression technique and Clustering algorithm to build predictive models for the Pareto fronts using a training task graph dataset. Experiments show that our approach can achieve large leakage savings for both synthetic and real-life applications with acceptable extended deadline. Furthermore, different variants of the proposed approach can reduce leakage power by 40-65% when compared to a performance-driven approach and by 15-43% when compared to state-of-the-art works. It's also proven that our Machine Learning Optimization framework can estimate the Pareto front for new coming task graphs 10x faster than well-established GA approach with only 10% degradation in quality. (C) 2016 Elsevier B.V. All rights reserved.
机译：晶体管尺寸的缩小使我们能够将越来越多的逻辑元件集成到FPGA芯片中，从而提高了计算能力。但是，这也严重影响了FPGA器件的泄漏功耗。 FPGA泄漏功率耗散的主要原因之一是利用预取技术来最大限度地减少部分可重配置（PR）FPGA的重配置开销（延迟）。该技术会在任务的重新配置和执行部分之间产生延迟，这可能导致FPGA泄漏功率高达38％，因为包含重新配置信息的SRAM单元无法掉电。在这项工作中，已经提出了一种包含调度，放置和放置后阶段的资源管理方法（RMA），以解决上述问题。在调度阶段，导出泄漏感知优先级函数以应对泄漏功率。放置阶段使用成本函数，允许设计人员确定性能与节省泄漏之间的期望折衷。放置后阶段采用启发式方法来缩小重新配置和任务执行之间的差距，从而进一步减少泄漏浪费。为了进一步检查性能（时间表长度）和泄漏浪费之间的平衡，我们提出了一个框架，利用遗传算法（GA）探索设计空间并获得Pareto最佳设计点。为了解决GA的耗时限制，我们使用回归技术和聚类算法使用训练任务图数据集为Pareto前沿建立了预测模型。实验表明，在可接受的延长期限内，我们的方法可为合成和实际应用节省大量泄漏。此外，与性能驱动的方法相比，提议的方法的不同变体可以将泄漏功率降低40-65％，与最新技术相比，可以降低15-43％。也已经证明，我们的机器学习优化框架可以将新出现的任务图的Pareto前沿估计为比公认的GA方法快10倍，而质量仅下降10％。 （C）2016 Elsevier B.V.保留所有权利。

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