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Implementation-aware selection of the custom instruction set for extensible processors

机译:对可扩展处理器的自定义指令集的实现感知选择

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This paper presents an approach for incorporating the effect of various logic synthesis options and logic level implementations into the custom instruction (CI) selection for extensible processors. This effect translates into the availability of a piecewise continuous spectrum of delay versus area choices for each CI, which in turn influences the selection of the CI set that maximizes the speedup per area cost (SPA) metric. The effectiveness of the proposed approach is evaluated by applying it to several benchmarks and comparing the results with those of a conventional technique. We also apply the methodology to the existing serialization algorithms aimed at relaxing register file constraints in multi-cycle custom instruction design. The comparison shows considerable improvements in the speedup per area compared to the custom instruction selection algorithms under the same area-budget constraint.
机译:本文提出了一种将各种逻辑综合选项和逻辑级别实现的效果整合到可扩展处理器的自定义指令(CI)选择中的方法。此效果转化为每个CI的延迟与区域选择的分段连续频谱的可用性,进而影响了CI集的选择,从而最大程度提高了单位面积成本(SPA)度量标准。通过将其应用于多个基准并将结果与​​常规技术的结果进行比较,可以评估所提出方法的有效性。我们还将这种方法应用于现有的序列化算法,旨在缓解多周期定制指令设计中的寄存器文件约束。对比显示,与相同区域预算约束下的自定义指令选择算法相比,每个区域的速度都有了显着提高。

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