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首页> 外文期刊>Microprocessors and microsystems >A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl
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A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl

机译：高速统一硬件体系结构，用于128位和256位AES和SHA-3候选Grostl安全级别

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摘要

One of the five final SHA-3 candidates, Grastl, has been inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grastl-AES computational efficiency (high-level scheduling, internal pipelining, resource sharing, etc.), we designed a high-speed coprocessor for the Grestl-based HMAC and AES in the counter mode. This coprocessor offers high-speed computations of both authentication and encryption/decryption with relatively small penalty in terms of area and speed when compared to the authentication (original Grastl circuitry) functionality only. From our perspective, the main advantage of Grastl over other finalists is the fact that its hardware architecture naturally accommodates AES at the cost of a small area overhead.
机译：最终的SHA-3候选方案中的五个候选方案之一是Grastl，它受到了高级加密标准的启发。此独特功能可在多种实际应用中加以利用。为了更好地了解Grastl-AES的计算效率（高级调度，内部流水线，资源共享等），我们在计数器模式下为基于Grestl的HMAC和AES设计了一个高速协处理器。与仅与身份验证（原始Grastl电路）功能相比，该协处理器可以在面积和速度方面以相对较小的代价提供身份验证和加密/解密的高速计算。从我们的角度来看，与其他决赛入围者相比，Grastl的主要优势在于以下事实：其硬件架构自然可以容纳AES，而代价是占用的面积较小。

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