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ELE0N3LP - Superscalar and low-power enhancements of single issue general purpose processor model

机译:ELE0N3LP-单发行通用处理器模型的超标量和低功耗增强功能

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Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents the modified LE0N3 processor IP core as an exemplary process of enhancing single issue general purpose processor with superscalar abilities and low-power features. The results of this work can be applied to many existing general purpose processor models to achieve low-power and high-performance systems suitable for modern embedded applications. In comparison with the original LE0N3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incorporated power domains. The Enhanced LE0N3 IP core was synthesized for 500 MHz using UMC 90 nm CMOS technology. Performed gate level VCD-based (Value Change Dump) power estimation shows that combining superscalar and low-power techniques allows performing faster program execution with less energy consumption than the original design.
机译:低功耗和高性能是现代嵌入式片上系统(SoC)设计中的最重要因素。计算复杂性的增加和时钟频率的不断增长表明动态和智能地利用可用硬件资源的必要性。本文提出了改进的LE0N3处理器IP内核,作为增强具有超标量功能和低功耗功能的单发行通用处理器的示例过程。这项工作的结果可以应用于许多现有的通用处理器模型,以实现适合现代嵌入式应用的低功耗和高性能系统。与原始的LE0N3 IP内核相比,新的内核每个周期最多可以执行两条指令,并动态管理合并的电源域。增强型LE0N3 IP内核使用UMC 90 nm CMOS技术合成了500 MHz。执行的基于VCD的门级VCD(值变化转储)功率估算表明,与原始设计相比,将超标量技术和低功率技术相结合可实现更快的程序执行速度和更少的能耗。

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