Scalable matrix decompositions with multiple cores on FPGAs

Yi-Gang Tai; Chia-Tien Dan Lo; Kleanthis Psarris

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Scalable matrix decompositions with multiple cores on FPGAs

机译：FPGA上具有多个内核的可扩展矩阵分解

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摘要

Hardware accelerators are getting increasingly important in heterogeneous systems for many applications, including those that employ matrix decompositions. In recent years, a class of tiled matrix decomposition algorithms has been proposed for out-of-memory computations and multi-core architectures including GPU-based heterogeneous systems. However, on FPGAs these scalable solutions for large matrices are rarely found. In this paper we use the latest tiled decomposition algorithms from high performance linear algebra for off-chip memory access and loop mapping on multiple processing cores for on-chip computation to perform scalable and high performance QR and LU matrix decompositions on FPGAs.

机译：硬件加速器在异构系统中对于许多应用（包括采用矩阵分解的应用）越来越重要。近年来，针对内存不足计算和包括基于GPU的异构系统在内的多核体系结构，提出了一种平铺矩阵分解算法。但是，在FPGA上很少找到这些适用于大型矩阵的可扩展解决方案。在本文中，我们使用高性能线性代数的最新切片分解算法进行片外存储器访问，并在多个处理内核上进行循环映射以进行片上计算，从而在FPGA上执行可扩展的高性能QR和LU矩阵分解。

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来源
《Microprocessors and microsystems》 |2013年第8ptab期|887-898|共12页
作者
Yi-Gang Tai; Chia-Tien Dan Lo; Kleanthis Psarris;
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作者单位

Department of Computer Science, The University of Texas at San Antonio, San Antonio, TX 78249, USA;

Department of Computer Science and Software Engineering, Southern Polytechnic State University, Marietta, GA 30060, USA;

School of Natural and Behavioral Science, City University of New York - Brooklyn College, Brooklyn, NY 11210, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Matrix decomposition; FPGA; Hardware accelerator; Linear algebra; Parallel algorithm; Multi-core architecture;

机译：矩阵分解;FPGA;硬件加速器;线性代数并行算法多核架构;

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2. Prototype Implementation of Array-Processor Extensible over Multiple FPGAs for Scalable Stencil Computation [J] . Kentaro SANO, WANG Luzhou, Satoru YAMAMOTO Computer architecture news . 2010,第4期

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Scalable matrix decompositions with multiple cores on FPGAs

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