• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Microprocessors and microsystems >Design of massively parallel hardware multi-processors for highly-demanding embedded applications
【24h】

Design of massively parallel hardware multi-processors for highly-demanding embedded applications

机译：面向高度嵌入式应用的大规模并行硬件多处理器设计

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Many new embedded applications require complex computations to be performed to tight schedules, while at the same time demanding low energy consumption and low cost. For implementation of these highly-demanding applications, highly-optimized application-specific multi-processor system-on-a-chip (MPSoCs) are required involving hardware multi-processors to execute the critical computations. The multi-processor accelerator design for such applications has to adequately resolve several difficult issues. Since the processors' micro- and macro-architectures, as well as, the memory and communication architectures are strongly interrelated, they have to be designed in combination. Complex mutual tradeoffs have to be resolved among the processor micro- and macro-architecture, and the corresponding memory and communication architectures, as well as, among the performance, power consumption and area. Unfortunately, the design methods and tools published till now do not address most of the design issues of the massively parallel hardware multi-processor accelerators. This paper discusses our novel quality-driven model-based multi-processor accelerator design method that adequately addresses the architecture design issues of hardware multi-processors for the modern highly-demanding embedded applications. Using the design of LDPC decoders for the latest high-speed communication system standards as an example application, we performed an extensive experimental research of the multi-processor design issues, and of our method and its design space exploration (DSE) framework. The experiments clearly demonstrated the existence of various complex architecture tradeoffs that could only be resolved through an adequate quality-driven combined design space exploration of the processors' micro- and macro-architectures, and the corresponding memory and communication architectures, as delivered by our method.
机译：许多新的嵌入式应用程序要求复杂的计算以严格的时间表执行，同时要求低能耗和低成本。为了实现这些高要求的应用程序，需要高度优化的特定于应用程序的多处理器片上系统（MPSoC），其中涉及硬件多处理器来执行关键计算。用于此类应用的多处理器加速器设计必须充分解决几个难题。由于处理器的微体系结构和宏体系结构以及内存和通信体系结构密切相关，因此必须将它们进行组合设计。复杂的相互折衷必须在处理器的微架构和宏架构以及相应的内存和通信架构之间以及性能，功耗和面积之间进行解决。不幸的是，迄今为止发布的设计方法和工具并未解决大规模并行硬件多处理器加速器的大多数设计问题。本文讨论了我们新颖的基于质量驱动的基于模型的多处理器加速器设计方法，该方法充分解决了针对现代高要求嵌入式应用的硬件多处理器的体系结构设计问题。以针对最新高速通信系统标准的LDPC解码器设计为例，我们对多处理器设计问题，我们的方法及其设计空间探索（DSE）框架进行了广泛的实验研究。实验清楚地表明，存在各种复杂的架构折衷，只有通过我们的方法所提供的对处理器的微架构和宏架构以及相应的内存和通信架构进行适当的质量驱动的组合设计空间探索，才能解决这些折衷方案。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号