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A study of 3D Network-on-Chip design for data parallel H.264 coding

机译:数据并行H.264编码的3D片上网络设计研究

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摘要

In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 2D design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.
机译:在本文中,我们实现,分析和比较了不同的片上网络(NoC)架构,旨在提高MPEG-4 / H.264编码的效率。分析了基于非统一缓存访问(NUCA)的二维(2D)和三维(3D)NoC。我们使用具有实际工作负载的完整系统模拟器来呈现结果。实验表明,与2D设计相比,两个3D NoC的平均网络等待时间分别减少了28%和34%。还显示出散热是改善3D芯片性能的折衷方案。我们的分析和实验结果为为数据并行H.264编码应用设计有效的3D NoC提供了指导。

著录项

  • 来源
    《Microprocessors and microsystems》 |2011年第7期|p.603-612|共10页
  • 作者单位

    Department of Information Technology, University of Turku, Joukahaisenkatu 3-5B, Turku 20520, Finland,Turku Center for Computer Science, Joukahaisenkatu 3-5B, 6th Floor, Turku 20520, Finland;

    Department of Information Technology, University of Turku, Joukahaisenkatu 3-5B, Turku 20520, Finland,Turku Center for Computer Science, Joukahaisenkatu 3-5B, 6th Floor, Turku 20520, Finland;

    Department of Information Technology, University of Turku, Joukahaisenkatu 3-5B, Turku 20520, Finland,Turku Center for Computer Science, Joukahaisenkatu 3-5B, 6th Floor, Turku 20520, Finland;

    Department of Information Technology, University of Turku, Joukahaisenkatu 3-5B, Turku 20520, Finland,Turku Center for Computer Science, Joukahaisenkatu 3-5B, 6th Floor, Turku 20520, Finland;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    network-on-chip; 3D IC design; H.264; coding; data parallel;

    机译:片上网络3D IC设计;H.264;编码;数据并行;

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