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FPGA architecture for fast parallel computation of co-occurrence matrices

机译:用于共现矩阵的快速并行计算的FPGA体系结构

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This paper presents a novel architecture for fast parallel computation of co-occurrence matrices in high throughput image analysis applications for which time performance is critical. The architecture was implemented on a Xilinx Virtex-XCV2000E-6 FPGA using VHDL. The symmetry and sparseness of the co-occurrence matrices are exploited to achieve improved processing times, and smaller, flexible area utilization as compared with the state of the art. The performance of the proposed architecture is evaluated using input images of various dimensions, in comparison with an optimized software implementation running on a conventional general purpose processor. Simulations of the architecture on contemporary FPGA devices show that it can deliver a speedup of two orders of magnitude over software.
机译:本文提出了一种新的体系结构,用于在时间性能至关重要的高吞吐量图像分析应用中快速并行计算共现矩阵。该架构是在使用VHDL的Xilinx Virtex-XCV2000E-6 FPGA上实现的。与现有技术相比,利用共现矩阵的对称性和稀疏性可以缩短处理时间,并具有较小的灵活区域利用率。与在常规通用处理器上运行的优化软件实现相比,使用各种尺寸的输入图像评估了所提出体系结构的性能。在当代FPGA器件上对体系结构的仿真表明,与软件相比,它可以提供两个数量级的加速。

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