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An efficient design of Quantum-dot Cellular Automata based 5-input majority gate with power analysis

机译：基于量子点元胞自动机的5输入多数门的高效设计与功率分析

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Quantum-dot Cellular Automata (QCA) are among the alternative technologies that enable nanoscale circuit design of high performance and low power consumption features. This work showcases an extensive structural and power analysis of previous 5-input majority gates. We found that the existing 5-input majority gates are not power efficient, and the structures are not well optimized. To overcome this, we proposed a new low-complexity coplanar 5-input majority gate, which consumes less power compared to prior designs. A novel 1-bit full adder circuit is presented to evaluate the suitability of the proposed gate. The results demonstrate that the proposed full adder performs equally well compared to existing multilayer designs, and performs better in the case of previous coplanar full adder designs in all aspects. Our design achieves 22% reduction in cell count and takes 18% less area in comparison to the best single layer design. Furthermore, it produces an equal delay, when compared to the best design in this segment. The QCADesigner tool is used to validate the layout of the proposed designs and the QCAPro power estimator tool is used to evaluate the power dissipation of all considered designs. Our results clearly demonstrate that, the hardware requirement for a QCA design is reduced and circuits become simpler in level, gate counts and clock phases by considering proposed gate.
机译：量子点元胞自动机（QCA）是使纳米级电路设计具有高性能和低功耗特性的替代技术之一。这项工作展示了以前的5输入多数门的广泛结构和功率分析。我们发现现有的5输入多数门效率不高，并且结构没有得到很好的优化。为了克服这个问题，我们提出了一种新的低复杂度共面5输入多数门，与以前的设计相比，它消耗的功率更少。提出了一种新颖的1位全加法器电路，以评估所提出门的适用性。结果表明，与现有的多层设计相比，拟议的完全加法器性能相当好，并且在以前的共面完全加法器设计的所有方面都具有更好的性能。与最佳单层设计相比，我们的设计可将单元数量减少22％，并减少18％的面积。此外，与该细分市场中的最佳设计相比，它产生了相等的延迟。 QCADesigner工具用于验证建议设计的布局，而QCAPro功耗估算器工具用于评估所有考虑设计的功耗。我们的结果清楚地表明，通过考虑拟议的栅极，可以降低QCA设计的硬件要求，并使电路的电平，门数和时钟相位变得更简单。

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