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Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations

机译：基于LLC存储器步幅分布的快速DRAM访问延迟建模，无需详细模拟

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摘要

The last level cache (LLC) memory accessing patterns influence the DRAM performance significantly due to their determination on the DRAM Row buffer hit rates (RBH), which are highly related to the DRAM access latency. However, it is too difficult to accurately quantify these effects without the LLC memory accessing traces from detailed simulations.This paper proposes an analytical model of DRAM access latency based on the RBH analysis. By exploring the relationship between the LLC spatial localities (described with the LLC stride distribution in this paper) and different RBH cases, the unknown parameters of the model can be quantified. Instead of detailed simulations, the LLC stride distributions are deduced from the stride distributions extracted from the software trace and the LLC miss rate estimated by the multi-level cache behavior model in our prior works, which significantly decreases the time overhead of our model.Fifteen benchmarks, chosen from Mobybench 2.0, Mibench 1.0 and Mediabench II, are utilized to evaluate the model's accuracy. Compared to the results of full simulations by gem5 and DRAMSim2, the average error of our model is lower than 7%, while the prediction process can be sped up by 50 times on average. (C) 2018 Elsevier B.V. All rights reserved.
机译：由于最后一级高速缓存（LLC）存储器访问模式取决于DRAM行缓冲区命中率（RBH），因此对DRAM性能的影响很大，而后者与DRAM访问延迟密切相关。但是，如果不通过详细的仿真来从LLC存储器访问轨迹，则很难精确地量化这些影响。本文基于RBH分析提出了DRAM访问延迟的分析模型。通过探索LLC空间局部性（本文中用LLC步幅分布描述）与不同RBH情况之间的关系，可以对模型的未知参数进行量化。代替详细的模拟，LLC步幅分布是从我们的先前工作中从软件跟踪中提取的步幅分布以及多级缓存行为模型估计的LLC丢失率推导出来的，这大大减少了模型的时间开销。十五从Mobybench 2.0，Mibench 1.0和Mediabench II中选择基准，以评估模型的准确性。与gem5和DRAMSim2的完全仿真结果相比，我们模型的平均误差低于7％，而预测过程平均可加快50倍。 （C）2018 Elsevier B.V.保留所有权利。

著录项

  • 来源
    《Microprocessors and microsystems》 |2019年第2期|159-169|共11页
  • 作者

    Ling Ming; Shang Xiaojing; Ji Kecheng; Shi Longxing;

  • 作者单位

    Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing, Jiangsu, Peoples R China;

    Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing, Jiangsu, Peoples R China;

    Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing, Jiangsu, Peoples R China|Southeast Univ, Nanjing, Jiangsu, Peoples R China;

    Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing, Jiangsu, Peoples R China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    DRAM Performance; DRAM Access latency; Stride distribution; Row buffer hit rate;

    机译：DRAM性能;DRAM访问延迟;步幅分布;行缓冲区命中率;

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