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Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems

机译：超声扇区成像系统的周期窃取DMA阵列信号处理器的体系结构和FPGA原型

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Array Signal Processor (ASP) is widely used in antenna-array beamforming applications, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. In this paper, architecture and Field Programmable Gate Array (FPGA) Prototype of a Cycle Steeling Direct Memory Access (DMA) Digital Beamformer (DBF) for Ultrasound Sector Imaging Systems is proposed. The architecture is based on delay and sum and it requires Fine Delay (FD) and Coarse Delay (CD) values to steer and dynamically focus the array, and apodization weights to improve the directivity. To improve the Fine delay accuracy Minimum Mean Square Error (MMSE) interpolation filter is proposed and implemented. To support wide Field of View (FOV) steering, immense delay values are required and real-time computations are hard for high sampling rate systems. Also, the precomputed delay values require huge memory, which causes a significant increase in the ASP area. To solve this problem, a cycle stealing DMA controller based on Quad Serial Peripheral (QSPI) interface to load delay values from external flash without disturbing ASP processing has been proposed and realized. Moreover, for debuggability,the architecture supports custom JTAG debug interface logic and lock-up latch based Design for Testability (DFT) Scan chain for multiple clock domains. The paper also presents the design and implementation of an Ultrasound Sector Imaging System Prototype setup to emulate the ASP. Most of the existing research work in this area supports ultrasound echo acquisition to PC and processing. However, the designed prototype helps researchers to validate computationally complex Ultrasound signal processing algorithms like ASP on FPGA and further processing on PC. (C) 2018 Elsevier B.V. All rights reserved.
机译：阵列信号处理器（ASP）被广泛用于天线阵列波束成形应用中，例如RADAR，SONAR，医疗超声，多输入多输出（MIMO）等。本文中，介绍了架构和现场可编程门阵列（FPGA）提出了一种用于超声扇区成像系统的循环钢直接存储访问（DMA）数字波束形成器（DBF）的原型。该架构基于延迟和总和，它需要精细延迟（FD）和粗略延迟（CD）值来控制阵列并动态聚焦，还需要切趾权重来改善方向性。为了提高精细延迟精度，提出并实现了最小均方误差（MMSE）插值滤波器。为了支持宽视场（FOV）操纵，需要大量的延迟值，并且对于高采样率系统而言，实时计算非常困难。而且，预先计算的延迟值需要巨大的内存，这会导致ASP面积显着增加。为了解决这个问题，已经提出并实现了一种基于四路串行外设（QSPI）接口的周期盗用DMA控制器，该控制器从外部闪存加载延迟值而不会干扰ASP处理。此外，为了实现可调试性，该体系结构支持自定义JTAG调试接口逻辑和针对多个时钟域的基于锁性闩锁的可测试性设计（DFT）扫描链。本文还介绍了可模拟ASP的超声扇区成像系统原型设置的设计和实现。该领域中的大多数现有研究工作都支持对PC进行超声回波采集和处理。但是，设计好的原型可以帮助研究人员验证计算复杂的超声波信号处理算法，例如FPGA上的ASP和PC上的进一步处理。 （C）2018 Elsevier B.V.保留所有权利。

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