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SCAC: Weakly-coupled execution model for massively parallel systems

机译:SCAC:大规模并行系统的弱耦合执行模型

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This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those of computation in order to facilitate their overlapping, thus covering the data transfer time. To allow the simultaneous execution of these phases, we propose an approach based on three levels : two globally-centralized/locally-distributed hierarchical control levels and a parallel computation level. A generic and parametric implementation of the SCAC model was performed to fit different applications. This implementation allows the designer to choose the system components (from pre-designed ones) and to set its parameters in order to build the adequate SCAC configuration for the target application. An analytical estimation is proposed to predict the execution time of an application running in SCAC mode, in order to facilitate the parallel program design and the SCAC architecture configuration. The SCAC model was validated by simulation, synthesis and implementation on an FPGA platform, with different examples of parallel computing applications. The comparison of the results obtained by the SCAC model with other models has shown its effectiveness in terms of flexibility and speed-up.
机译:这项工作为大规模并行系统提出了一个执行模型,旨在通过计算确保通信重叠。该模型称为SCAC:同步通信异步计算。这种弱耦合模型将通信阶段的执行与计算阶段分开,以促进它们的重叠,从而覆盖了数据传输时间。为了允许同时执行这些阶段,我们提出了一种基于三个级别的方法:两个全局集中/本地分布的层次控制级别和一个并行计算级别。为了适应不同的应用,对SCAC模型进行了通用和参数化的实现。此实现使设计人员可以选择系统组件(从预先设计的组件中)并设置其参数,以便为目标应用程序构建适当的SCAC配置。为了便于并行程序设计和SCAC体系结构配置,提出了一种分析估计来预测以SCAC模式运行的应用程序的执行时间。 SCAC模型已通过在FPGA平台上的仿真,综合和实现进行了验证,并带有并行计算应用程序的不同示例。 SCAC模型与其他模型获得的结果的比较表明,它在灵活性和提速方面是有效的。

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