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A new design and implementation of hardware accelerator for line detection

机译：用于线路检测的硬件加速器的新设计和实现

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摘要

Linear detection algorithms require a series of sequential and complex process that needs high-performance processors to reduce computing time when the software is implemented. In this paper, we design a linear detection hardware accelerator with parallel computing capability through our proposed pipelined multiprocessor system-on-a-chip (SoC) design methodology; it contains an upper pipelined controller that controls the operation of the underlying Canny edge detection module and the Hough transform module. That is, we first use the edge detection module to get the edge information, and then use Hough transform to improve the accuracy of linear detection results. Finally, the pipeline control is adopted to enhance the effectiveness of the module. Based on the Canny process and the Gaussian blurring method, this study can reduce the false detection caused by noise, and decrease the number of operations and resource usage without affecting the straight line detection. Compared with Xu and Chen [14] [21] [34] [35], the proposed method can reduce 84% and 74% of the circuit resources, respectively. The hardware function circuit generated from our methodology has a good decentralized architecture and scalability, and it is easier to use in all kinds of embedded systems.
机译：线性检测算法需要一系列顺序和复杂的过程，这些过程需要高性能处理器来减少软件实施时的计算时间。在本文中，我们通过我们提出的流水线多处理器片上系统（SoC）设计方法，设计了具有并行计算功能的线性检测硬件加速器；它包含一个上层流水线控制器，用于控制基础Canny边缘检测模块和Hough变换模块的操作。也就是说，我们首先使用边缘检测模块获取边缘信息，然后使用霍夫变换来提高线性检测结果的准确性。最后，采用流水线控制来提高模块的有效性。该研究基于Canny过程和高斯模糊方法，可以减少由噪声引起的错误检测，并减少运算次数和资源使用量，而不会影响直线检测。与Xu和Chen [14] [21] [34] [35]相比，该方法可分别减少84％和74％的电路资源。通过我们的方法生成的硬件功能电路具有良好的分散架构和可扩展性，并且更易于在各种嵌入式系统中使用。

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