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Serialized lightweight SHA-3 FPGA implementations

机译：序列化的轻型SHA-3 FPGA实现

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In this article, we extend our study of lightweight FPGA implementations of SHA-3 published at ReConFig 2016. We use the shallow pipeline optimization technique for the slice-oriented SHA-3 architecture developed previously and examine additional aspects. Firstly, we adapt the implementation to the state organization proposed by Winderickx et al. based on shift register primitives available on Xilinx FPGA platforms. Secondly, we study the usage of block RAM instead of distributed RAM for the original designs. The shallow pipeline optimization already has reduced the area to about 90 slices for both Virtex-5 and Virtex-6 FPGAs. This is a significant improvement over the previous state of the art.On the one hand, our additional results show that the optimized state representation by Windericks et al. using shift registers does not improve the performance at all, compared to the solution based on distributed RAM. The main reason for this is the implementation of the p function, which requires different offsets for the rotations to be implemented and also larger shift registers for most lanes than the 64 bits of a lane. Together, this leads to a higher than expected area consumption for the shift register approach, which leads to a very similar total area consumption than the RAM based approach. On the other hand, the block RAM solution shows a considerable reduction of the slice utilization from about 88 to only 54 slices at the expense of 13 to 14 block RAMs. However, at the same time the achievable maximum clock frequency is considerably lower, because of the additional routing delays from and to the block RAM. (C) 2019 Elsevier B.V. All rights reserved.
机译：在本文中，我们扩展了在ReConFig 2016上发布的SHA-3轻量级FPGA实现的研究。我们对先前开发的面向切片的SHA-3架构使用了浅管线优化技术，并研究了其他方面。首先，我们将实施方案适应于温德瑞克斯等人提出的国家组织。基于Xilinx FPGA平台上可用的移位寄存器原语。其次，我们研究了原始设计中使用Block RAM代替分布式RAM的用法。浅层流水线优化已经将Virtex-5和Virtex-6 FPGA的面积减小到大约90片。这是对现有技术水平的重大改进。一方面，我们的其他结果表明，Windericks等人的优化状态表示。与基于分布式RAM的解决方案相比，使用移位寄存器根本不会提高性能。这样做的主要原因是p函数的实现，该函数需要不同的偏移量来实现旋转，并且大多数通道的移位寄存器都比通道的64位大。总体而言，这导致移位寄存器方法的区域消耗高于预期，这导致与基于RAM的方法非常相似的总区域消耗。另一方面，Block RAM解决方案显示条带利用率从大约88个条带大幅减少到仅54个条带，但代价是13到14个Block RAM。但是，与此同时，由于往返于Block RAM的额外路由延迟，可达到的最大时钟频率要低得多。 （C）2019 Elsevier B.V.保留所有权利。

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