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首页> 外文期刊>Microprocessors and microsystems >Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap
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Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap

机译：使用具有氧化物重叠的异质连接隧道晶体管的低功率7T SRAM单元的装置和电路电平设计，表征和实现

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The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, electronic systems. In place of MOS transistor, which is homojunction, if a heterojunction transistor with low bandgap materials used, the subthreshold swing of the transistor being reduce to below 60 mV/decade and low leakage current can obtain. Ge, GeSi, etc. materials are used in the design and implementation Heterojunction Tunneling Transistor (HETT) due to low band gap.In this work, both types of HETTs such as NHETT and PHETT designed and implemented using low bandgap materials with a technique of increasing tunneling area by overlapping. The performance of NHETT and PHETT described by the design and implementation of 7T MOSFET SRAM. The power and delay analysis of this SRAM cell using HETTs presented, and the results compared with MOSFET based standard 6T, conventional 7T SRAM cells. (c) 2020 Elsevier B.V. All rights reserved.
机译：由于MOS晶体管的亚阈值摆动的限制而受限制的设备缩放，其不小于60 mV / DEC。研究人员更多地专注于高级，更具特色，电子系统的功率高效技术。代替MOS晶体管，该晶体管是同质连接的，如果使用具有低带隙材料的异质结晶体管，晶体管的亚阈值摆动降低到低于60 mV /十年，并且可以获得低漏电流。 GE，GESI等材料用于设计和实现异质结隧道晶体管（HETT）由于低频带隙而导致的隧道晶体管（HETT）。在这项工作中，使用带有低带隙材料的NHETT和PHETT的两种类型的佩莱斯（如NHETT和PHET）使用具有技术的技术通过重叠增加隧道区域。 7T MOSFET SRAM的设计和实现描述的NHETT和PHET的性能。使用HETTS提出的SRAM单元的功率和延迟分析，结果与基于MOSFET的标准6T，常规7T SRAM细胞相比。 （c）2020 Elsevier B.v.保留所有权利。

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