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Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

机译：实时FPGA实现高速和面积优化的哈里斯角检测算法

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摘要

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area (smaller gate count on target FPGA) and speed for the same target board.
机译：哈里斯角检测是一种经常用于图像处理和计算机视觉应用的算法，用于检测输入图像中的角落。在图像处理的大多数现代应用中，需要实时实现诸如现场可编程门阵列（FPGA）的硬件系统中的哈里斯角检测等驻地检测等算法。 FPGA允许更快的算法吞吐量，这是需要匹配实时速度或需要处理更快数据速率的情况的情况。高级综合工具为设计人员提供更高的抽象级别，在设计流程期间继续验证，因此正在与设计社区流行。本文提出了哈里斯角检测算法的高速和面积优化实现。拟议的实施是使用基于应用特定于中间数据节点的应用特定位宽度的新型高级合成（HLS）设计方法实现。使用Matlab HDL编码器为HLS生成寄存器传输级别（RTL）代码。生成的硬件描述语言（HDL）代码在Xilinx Zedboard上使用Vivado软件实现，并在实时验证了输入视频流。所得结果优于先前实现的实施方案（目标FPGA的较小栅极计数）和相同目标板的速度。

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