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Linear and quadratic time frequency transforms on FPGA using folding technique

机译：使用折叠技术对FPGA的线性和二次时间频率变换

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摘要

In this paper time frequency representations (TFRs) are implemented on FPGA. Linear TFRs such as Short Time Fourier Transform (STFT), Continuous Wavelet Transform (CWT), Stockwell Transform (S-Transform) and Quadratic TFRs like Wigner Ville Distribution (WVD), Pseudo Wigner Ville Distribution (PWVD), Choi William Distribution (CWD), and Rihaczek Distribution (RD) are designed in Verilog and performed over FPGA. In most of the FFT architectures many butterfly unit (BU) stages are remains idle during computation since current stage computation depends on previous stage outputs. As a result these idle BU leads to additional register allocation and delay propagation. An optimized VLSI architecture is proposed in this paper for efficient clock utilization to compute FFT in all TFRs. Folding technique is implemented in all TFRs to minimize the register allocation. The design is carried out in Verilog code and CORDIC algorithm is used tocomputecorebutterflystructureofFFTinallTFRs. Chirp signal is taken as input to evaluate real time performances of all TFRs. Real time factors utilized on FPGA hardware like Flip Flops, IOBs, LUTs utilization and power consumption are compared for allTFRs. Further proposed methodology is compared with previous existing methods for better time frequency applications.
机译：在本文中，时间频率表示（TFR）在FPGA上实现。线性TFR，如短时间傅里叶变换（STFT），连续小波变换（CWT），储存普通变换（S-Transform）和像Wigner Ville Distribution（WVD），伪Wigner Ville Distribution（PWVD），Choi William Passion（CWD）等二次TFR ），Rihaczek分布（RD）在Verilog中设计并在FPGA上进行。在大多数FFT架构中，许多蝶形单元（BU）级在计算期间保持空闲，因为当前阶段计算取决于先前的阶段输出。结果，这些空闲引导导致额外的寄存器分配和延迟传播。本文提出了一种优化的VLSI架构，以便有效时钟利用率来计算所有TFR中的FFT。折叠技术在所有TFR中实现以最小化寄存器分配。该设计在Verilog代码中执行，Cordic算法用于ComputeCoreButterflyStructureOffftinallTFRS。 Chirp信号被视为输入以评估所有TFR的实时性能。与ALLTFRS进行比较了FPGA硬件等FPGA硬件上使用的实时因素，以ALLFRS进行比较。将进一步提出的方法与先前的现有方法进行比较，以便更好的时间频率应用。

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