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首页> 外文期刊>Microwaves, Antennas & Propagation, IET >About 250/285 GHz push–push oscillator using differential gate equalisation in digital 65-nm CMOS
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About 250/285 GHz push–push oscillator using differential gate equalisation in digital 65-nm CMOS

机译:约250/285 GHz推挽振荡器,在数字65nm CMOS中使用差分门均衡

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This study presents a push-push oscillator architecture based on differential gate equalisation to enhance the oscillation frequency while providing relatively high output power with ultra-compact layout form factor. The frequency enhancement is derived as a function of the equivalent RLC model of the oscillator's main constituents. The proposed principle is applied to a terahertz oscillator in the 200-300 GHz range to mitigate the excessive substrate and skin effect losses in standard digital 65-nm complementary metal-oxide-semiconductor technology at such high frequencies. The design concept is validated using two single-stage push-push oscillators. The first oscillator shows -8.1 dBm output power at 250 GHz oscillation frequency and -106.8 dBc/Hz phase noise at 10 MHz offset while consuming 76 mW power from 1.5 V DC supply voltage. The chip area is 200 x 250 mu m(2). The second oscillator provides -14.8 dBm output power at 285 GHz and -106 dBc/Hz phase noise at 10 MHz offset with 80 mW power consumption from 1.5 V DC supply. The chip area is 200 x 200 mu m(2).
机译:这项研究提出了一种基于差分门均衡的推挽振荡器架构,以提高振荡频率,同时以超紧凑的布局尺寸提供相对较高的输出功率。频率增强是根据振荡器主要成分的等效RLC模型得出的。所提出的原理适用于200-300 GHz范围内的太赫兹振荡器,以减轻标准数字65 nm互补金属氧化物半导体技术在如此高的频率下产生的过多衬底和集肤效应损耗。使用两个单级推挽振荡器对设计概念进行了验证。第一个振荡器在250 GHz振荡频率下显示-8.1 dBm输出功率,在10 MHz偏移下显示-106.8 dBc / Hz相位噪声,同时从1.5 V DC电源电压消耗76 mW功率。芯片面积为200 x 250微米(2)。第二个振荡器在285 GHz时提供-14.8 dBm的输出功率,在10 MHz偏移时提供-106 dBc / Hz的相位噪声,而1.5 V DC电源的功耗为8​​0 mW。芯片面积为200 x 200微米(2)。

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