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首页> 外文期刊>Motion Imaging Journal, SMPTE >A Design Approach to Creating Scalable Video Processing Systems beyond UHDTV1 on an FPGA
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A Design Approach to Creating Scalable Video Processing Systems beyond UHDTV1 on an FPGA

机译:在FPGA上创建超越UHDTV1的可扩展视频处理系统的设计方法

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摘要

An unquenchable end-user thirst for enhanced video quality results in ever-scaling video frame size and frame rate requirements. As we move from UHDTV1 to UHDTV2 and 120 frames/sec to 300 frames/sec, inevitably the computational complexity of video processing systems required to consume, process, and deliver video content increases. The need for solutions to support combinations of frame sizes and rates, as well as future increments, emphasizes the need for system scalability. The computational complexity and scalability requirements pose exciting challenges for field-programmable gate array (FPGA) implementation of video processing pipelines. This paper presents implementation techniques and methodologies to overcome these challenges. We specifically concentrate on architectures whereby the input per-pixel video sample rate exceeds the system clock rate. Novel results include classifying pixel processing orders and presenting a component-based design approach for future-proofing video processing solutions against an ever-scaling computational complexity requirement. Resource and memory bandwidth requirements of such systems are also analyzed and trends are presented.
机译:最终用户对增强视频质量的渴求导致视频帧尺寸和帧速率要求不断提高。随着我们从UHDTV1到UHDTV2以及从120帧/秒到300帧/秒的发展,不可避免地,消费,处理和交付视频内容所需的视频处理系统的计算复杂性会增加。需要支持帧大小和速率以及未来增量组合的解决方案的需求强调了系统可伸缩性的需求。计算复杂性和可伸缩性要求给视频处理管道的现场可编程门阵列(FPGA)实现带来了令人兴奋的挑战。本文介绍了克服这些挑战的实施技术和方法。我们特别专注于输入每像素视频采样率超过系统时钟率的体系结构。新颖的结果包括对像素处理顺序进行分类,并针对日益增长的计算复杂性要求提出一种基于组件的设计方法,以用于面向未来的视频处理解决方案。还分析了此类系统的资源和内存带宽需求,并提出了趋势。

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