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A hierarchical multiplier-free architecture for HEVC transform

机译：HEVC变换的无分层乘数架构

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摘要

In spite of high decorrelation performance, the large block size of transform coding in High Efficiency Video Coding (HEVC) brings about undesirable complexity in hardware design. The heaviest burden in HEVC transform implementation is the large quantity of multiplications. In this paper, we propose a novel hierarchical multiplier-free architecture for HEVC transform, which can achieve a multiplier-free partial butterfly combined with matrix multiplications (PBMM) architecture based on vector decomposition (VD-PBMM). In the proposed architecture, the complicate matrix multiplication in PBMM is achieved by several simple stages to simplify its VLSI realization. Each stage only involves additions and multiplications with power of two which can be achieved by shifters and adders. In addition, the new architecture can balance the distribution of adders to improve the system frequency. The proposed architecture has been evaluated with TSMC 0.13um CMOS technology. The relative system can run at 400 MHz with 92 K logic gates, which is about half of the PBMM method when the latency is 8. The proposed architecture can achieve the transform without any performance loss compared with the standard, and it is suitable for the hardware implementation in VLSI design.
机译：尽管具有高的去相关性能，但高效视频编码（HEVC）中变换编码的大块大小在硬件设计中带来了不良的复杂性。 HEVC转换实现中最重的负担是大量的乘法。在本文中，我们提出了一种用于HEVC变换的新颖的无分层乘数架构，该架构可实现基于矢量分解（VD-PBMM）的无乘数局部蝶形结合矩阵乘法（PBMM）架构。在所提出的架构中，PBMM中的复杂矩阵乘法是通过几个简单的阶段来实现的，以简化其VLSI实现。每个阶段仅涉及加法器和乘法器，其乘方为二，可以通过移位器和加法器实现。另外，新架构可以平衡加法器的分布以提高系统频率。所提议的体系结构已通过TSMC 0.13um CMOS技术进行了评估。相对系统可以使用92 K逻辑门以400 MHz运行，这是等待时间为8时大约是PBMM方法的一半。与标准相比，所提出的体系结构可以实现转换而没有任何性能损失，并且适用于VLSI设计中的硬件实现。

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  • 来源
    《Multimedia Tools and Applications》 |2017年第1期|997-1015|共19页
  • 作者

    Fan Chunxiao; Li Fu; Shi Guangming; Niu Yi; Qi Fei; Xie Xuemei; Jiao Dandan;

  • 作者单位

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

    Xidian Univ, Sch Elect Engn, Key Lab Intelligent Percept & Image Understanding, Chinese Minist Educ, Xian, Peoples R China;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    DCT; HEVC; Multiplier-free; Transform coding;

    机译：DCT;HEVC;无乘数;变换编码;

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