Test results of ATLASPIX3 - A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

R. Schimassek; A. Andreazza; H. Augustin; M. Barbero; M. Benoit; F. Ehrler; G. Iacobucci; A. Meneses; P. Pangaud; M. Prathapan; A. Schoening; E. Vilella; A. Weber; M. Weber; W. Wong; H. Zhang; I. Peric

首页> 外文期刊>Nuclear Instruments & Methods in Physics Research. B, Beam Interactions with Materials and Atoms >Test results of ATLASPIX3 - A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

【24h】

Test results of ATLASPIX3 - A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

机译：ATLaspix3的测试结果 - 一种专为多芯片模块构造而设计的掩模版尺寸HVCMOS像素传感器

获取原文

获取原文并翻译 | 示例

获取外文期刊封面封底 >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0 × 2.1 cm~2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150 × 50 μm~2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.

机译：高电压CMOS像素传感器将被或被提出用于几种粒子物理实验，例如MU3E实验。 ATLaspix3是第一个全掩模版大小单片HVCMOS传感器，用于构造多芯片模块。使用案例的规范已从第五层中的Atlas像素升级中取出，其中它是候选者。芯片的大小为2.0×2.1cm〜2，周边在一侧，使芯片3侧按键。 ATLaspix3已在标准的180nm HVCMOS过程中实现。每个像素的面积为150×50μm〜2，并且包含作为深N-阱实现的大电荷收集电极。 N阱周围的耗尽量由高电压偏压和较高电阻率衬底的使用而放大。读出电子产品支持触发和触发器读数，零抑制。 Atlaspix3可用于在实验中构建CMOS模块，用于在需要高时分辨率，高辐射容差，低功耗和低材料预算的实验中进行粒子跟踪。在设计阶段，已经支付了特别注意，降低像素之间的时序差异和读出的速率能力。

著录项

来源
《Nuclear Instruments & Methods in Physics Research. B, Beam Interactions with Materials and Atoms》 |2021年第11期|164812.1-164812.5|共5页
作者
R. Schimassek; A. Andreazza; H. Augustin; M. Barbero; M. Benoit; F. Ehrler; G. Iacobucci; A. Meneses; P. Pangaud; M. Prathapan; A. Schoening; E. Vilella; A. Weber; M. Weber; W. Wong; H. Zhang; I. Peric;
展开▼
作者单位

Karlsruhe Institute of Technology (DE) Germany;

Universita degli Studi e INFN Milano (IT) Italy;

University Heidelberg (DE) Germany;

Aix Marseille Universiti CNRS/IN2P3 CPPM Marseille (FR) France;

Universiti de Geneve (CH) Switzerland;

Karlsruhe Institute of Technology (DE) Germany;

Universiti de Geneve (CH) Switzerland;

University Heidelberg (DE) Germany;

Aix Marseille Universiti CNRS/IN2P3 CPPM Marseille (FR) France;

Karlsruhe Institute of Technology (DE) Germany;

University Heidelberg (DE) Germany;

University of Liverpool (GB) United Kingdom;

Karlsruhe Institute of Technology (DE) Germany University Heidelberg (DE) Germany;

University of Bern (CH) Switzerland;

formerly of University of Geneva (CH) Switzerland;

Karlsruhe Institute of Technology (DE) Germany;

Karlsruhe Institute of Technology (DE) Germany;

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类
关键词
ATLASPIX; HVCMOS; MAPS; Timing optimisation;

机译：阿特拉斯卡;HVCMOS;地图;定时优化;

相似文献

外文文献
中文文献
专利

1. Test chips, test systems, and thermal test data for multichip modules in the ESPRIT-APACHIP project [J] . OMathuna S.C., Fromont T. IEEE transactions on components, packaging, and manufacturing technology. Part A . 1994,第3期

机译：ESPRIT-APACHIP项目中多芯片模块的测试芯片，测试系统和热测试数据
2. Design and testing of high-speed interconnects for superconducting multi-chip modules [J] . Narayana S., Semenov V.K., Polyakov Y.A., Superconductor Science & Technology . 2012,第10期

机译：用于超导多芯片模块的高速互连的设计和测试
3. Development of n-in-p silicon planar pixel sensors and flip-chip modules for very high radiation environments [J] . Y. Unno, Y. Ikegami, S. Terada, Nuclear Instruments & Methods in Physics Research . 2011,第1期

机译：开发适用于极高辐射环境的n-in-p硅平面像素传感器和倒装芯片模块
4. HVCMOS Pixel Detectors First Measurements on the Reticle Size Prototype for the ATLAS Pixel Layers [C] . Felix Ehrler, Ivan Peric, Rudolf Schimassek IEEE Nuclear Science Symposium . 2016

机译：HVCMOS像素检测器首先测量图表像素层的掩模版尺寸原型
5. Design for testability techniques and optimization algorithms for performance and functional testing of multichip module interconnections. [D] . Pendurkar, Rajesh Yashavant. 1999

机译：用于多芯片模块互连的性能和功能测试的可测试性技术和优化算法的设计。
6. An Image Signal Accumulation Multi-Collection-Gate Image Sensor Operating at 25 Mfps with 32 × 32 Pixels and 1220 In-Pixel Frame Memory [O] . Vu Truong Son Dao, Nguyen Ngo, Anh Quang Nguyen, 2018

机译：图像信号累积多采集门图像传感器以25 Mfps的速度运行具有32×32像素和1220像素内帧存储器
7. Single Photon Counting X-ray Imaging with Si and CdTe Single Chip Pixel Detectors and Multichip Pixel Modules [O] . Fischer, Peter, Krimmel, Sven, Krueger, Hans, 2003

机译：单光子计数X射线成像与si和CdTe单片像素探测器和多芯片像素模块

Test results of ATLASPIX3 - A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

摘要

著录项

相似文献

相关主题

期刊订阅