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Improving Cache Performance with Balanced Tag and Data Paths

机译：通过平衡的标记和数据路径提高缓存性能

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摘要

There are two concurrent paths in a typical cache access — one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. In both direct-mapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In this paper, we propose a path balancing technique to help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-G and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6% to 28% are possible.
机译：典型的高速缓存访​​问中有两个并发路径-一个通过数据数组，另一个通过标签数组。通过数据阵列的路径将选定的集合驱动出阵列。通过标签数组的路径确定高速缓存命中/未命中，对于集合关联的高速缓存，请从所选集合中选择适当的行。在直接映射和集合关联的高速缓存中，通过标签数组的路径比通过数据数组的路径长得多。在本文中，我们提出了一种路径平衡技术，以帮助匹配标签和数据路径的延迟。该技术背后的基本思想是采用标签阵列的单独子集来解耦地址标签和高速缓存行之间的一对一关系，从而实现提供更高性能的设计。使用TPC-G和SPEC92基准进行的性能评估表明，这种路径平衡技术相对于常规缓存设计在整体系统性能方面提供了令人印象深刻的改进。对于TPC-C，可以在6％到28％的范围内进行改进。

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