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Exploiting Dual Data-Memory Banks in Digital Signal Processors

机译：在数字信号处理器中开发双数据存储库

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Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through their use of specialized hardware features and small chip areas, DSPs provide the high performance necessary for embedded applications at the low costs demanded by the high-volume consumer market. One feature commonly found in DSPs is the use of dual data-memory banks to double the memory system's bandwidth. When coupled with high-order data interleaving, dual memory banks provide the same bandwidth as more costly memory organizations such as a dual-ported memory. However, making effective use of dual memory banks remains difficult, especially for high-level language (HLL) DSP compilers. In this paper, we describe two algorithms - compaction-based (CB) data partitioning and partial data duplication - that we developed as part of our research into the effective exploitation of dual data-memory banks in HLL DSP compilers. We show that CB partitioning is an effective technique for exploiting dual data-memory banks, and that partial data duplication can augment CB partitioning in improving execution performance. Our results show that CB partitioning improves the performance of our kernel benchmarks by 13%-40% and the performance of our application benchmarks by 3%-15%. For one of the application benchmarks, partial data duplication boosts performance from 3% to 34%.
机译：在过去的十年中，数字信号处理器（DSP）成为在大批量消费产品中实现嵌入式应用的首选处理器。通过使用专门的硬件功能和较小的芯片面积，DSP以大批量消费市场所需的低成本提供了嵌入式应用所需的高性能。 DSP中常见的一项功能是使用双数据存储区使存储系统的带宽增加一倍。当与高阶数据交织结合使用时，双存储体可以提供与更昂贵的存储组织（如双端口存储）相同的带宽。但是，有效利用双存储体仍然很困难，尤其是对于高级语言（HLL）DSP编译器而言。在本文中，我们描述了两种算法-基于压缩的（CB）数据分区和部分数据重复-我们在对HLL DSP编译器中有效利用双数据存储区进行研究的过程中开发了它们。我们表明，CB分区是一种利用双重数据存储库的有效技术，并且部分数据重复可以增强CB分区，从而提高执行性能。我们的结果表明，CB分区将内核基准的性能提高了13％-40％，将应用基准的性能提高了3％-15％。对于其中一个应用程序基准，部分数据重复将性能从3％提高到34％。

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