FPGA Realization of the LIRA Neural Classifier

Alejandro Vega; Tatiana Baidyk; Ernst Kussul; Jose Luis Perez Silva

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FPGA Realization of the LIRA Neural Classifier

机译：LIRA神经分类器的FPGA实现

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摘要

Different types of neural networks can be used to classify images. We propose to apply LIRA (Limited Receptive Area) neural classifier to work with images. To accelerate the neural network functioning we propose a digital implementation of the LIRA neural classifier. We begin with a neuron design, and then continue with the neural network simulation. The advantage of neural network is its parallel structure and possibility of the training. FPGA (Field Programmable Gate Array) allows the implementation of these parallel algorithms in a single device. Speed of classification is one of the most important requirements in adaptive control systems based on computer vision. The contribution of this article is LIRA neural classifier implementation with FPGA for two classes to accelerate the training and recognition processes.

机译：可以使用不同类型的神经网络对图像进行分类。我们建议应用LIRA（有限接受区）神经分类器处理图像。为了加速神经网络功能，我们提出了LIRA神经分类器的数字实现。我们从神经元设计开始，然后继续进行神经网络仿真。神经网络的优点是其并行的结构和训练的可能性。 FPGA（现场可编程门阵列）允许在单个设备中实现这些并行算法。分类速度是基于计算机视觉的自适应控制系统中最重要的要求之一。本文的贡献是使用FPGA的LIRA神经分类器实现了两个类，以加快训练和识别过程。

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来源
《Optical memory & neural networks》 |2011年第3期|p.168-180|共13页
作者
Alejandro Vega; Tatiana Baidyk; Ernst Kussul; Jose Luis Perez Silva;
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作者单位

Center of Applied Science and Technological Development, National Autonomous University of Mexico (UNAM), Circuito exterior s, Ciudad Universitaria, Coyoacan, 04510, Mexico City, D.F., Mexico;

Center of Applied Science and Technological Development, National Autonomous University of Mexico (UNAM), Circuito exterior s, Ciudad Universitaria, Coyoacan, 04510, Mexico City, D.F., Mexico;

Center of Applied Science and Technological Development, National Autonomous University of Mexico (UNAM), Circuito exterior s, Ciudad Universitaria, Coyoacan, 04510, Mexico City, D.F., Mexico;

Center of Applied Science and Technological Development, National Autonomous University of Mexico (UNAM), Circuito exterior s, Ciudad Universitaria, Coyoacan, 04510, Mexico City, D.F., Mexico;

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正文语种 eng
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关键词
LIRA neural classifier; logic circuits; neural networks; FPGA; neuron;

机译：LIRA神经分类器;逻辑电路;神经网络;FPGA;神经元;

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专利

1. LIRA neural classifier for handwritten digit recognition and visual controlled microassembly [J] . Ernst Kussul, Tatiana Baidyk Neurocomputing . 2006,第16a18期

机译：LIRA神经分类器，用于手写数字识别和视觉控制的微组件
2. O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices [J] . Haghi Pouya, Kamal Mehdi, Afzali-Kusha Ali, IEEE transactions on circuits and systems . I , Regular papers . 2020,第9期

机译：O⁴-DNN：一种基于混合DSP-LUT的处理单元，具有操作包装和超出执行，以便在FPGA设备上有效地实现卷积神经网络
3. FPGA Realization of Deep Neural Network for Hardware Trojan Detection [J] . Varun Reddy, Nirmala Devi M International Journal of Engineering & Technology . 2020,第3期

机译：FPGA实现硬件木马检测深神经网络
4. FPGA Based LIRA Neural Classifier [C] . Vega Alejandro, Baidyk Tatiana, Kussul Ernst, 2011 IEEE Electronics, Robotics and Automotive Mechanics Conference . 2011

机译：基于FPGA的LIRA神经分类器
5. Caffeinated FPGAs: FPGA Framework for Training and Inference of Convolutional Neural Networks With Reduced Precision Floating-Point Arithmetic [D] . DiCecco, Roberto. 2018

机译：含咖啡因的FPGA：用于训练和推理卷积神经网络的FPGA框架，具有降低的精度浮点算法
6. Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics [O] . Yutaro Iiyama, Gianluca Cerminara, Abhijay Gupta, 2020

机译：高能量物理实时粒子重建的FPGA距离加权图神经网络
7. FPGA Realization of Deep Neural Network for Hardware Trojan Detection [O] . Varun Reddy, Nirmala Devi M 2020

机译：FPGA实现硬件木马检测深神经网络

FPGA Realization of the LIRA Neural Classifier

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