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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >Evaluation of a Heterogeneous Multicore Architecture by Design and Test of an OFDM Receiver
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Evaluation of a Heterogeneous Multicore Architecture by Design and Test of an OFDM Receiver

机译：通过OFDM接收器的设计和测试评估异构多核架构

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This paper presents an evaluation of a Heterogeneous Multicore Architecture (HMA) by implementing Orthogonal Frequency-Division Multiplexing (OFDM) receiver blocks as designs for the test of functionality. OFDM receiver consists of computationally intensive and general-purpose processing tasks that can provide maximum coverage to test and evaluate a massively-parallel as well as a general-purpose platform like the HMA. The blocks of the receiver are primarily designed by crafting template-based Coarse-Grained Reconfigurable Array (CGRA) devices and then arranging them in a sequence over a Network-on-Chip (NoC) structure along with a few RISC cores for complete OFDM processing. The OFDM blocks such as Fast Fourier Transform (FFT) and Time Synchronization are computationally intensive and require parallel processing. The OFDM receiver also contains tasks such as frequency offset estimation which require the processing of Taylor series and CORDIC algorithms that are serial in nature. Such a combination of serial and parallel algorithms can perform a thorough exploration and evaluation of almost all the design features of an HMA. The OFDM implementation has led to scale CGRAs to different dimensions, instantiate Processing Elements (PEs) as multiple arithmetic resources and to establish almost all possible ways of PE interconnections. It further explores time-multiplexed patterns for data placement in the CGRA memories. Nevertheless, the data can also be exchanged among different nodes over NoC structure simultaneously and independently by using direct memory access devices. In this experimental work, the performance of each CGRA, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Today's HMAs are generally over or under resourced for the applications that they are designed for and thus not an optimal choice for the end user. Apart from the interesting comparisons to the other state-of-the-art, our experimental setup has provided important insight and guidelines that the designers can use to implement near-optimal solutions for their target applications.
机译：本文通过实现正交频分复用（OFDM）接收器模块作为功能测试的设计，对异构多核体系结构（HMA）进行了评估。 OFDM接收器由计算密集型和通用处理任务组成，这些任务可以提供最大的覆盖范围，以测试和评估大规模并行以及诸如HMA的通用平台。接收器模块的设计主要是通过设计基于模板的粗粒度可重配置阵列（CGRA）设备，然后将它们按顺序排列在片上网络（NoC）结构上，以及一些RISC内核，以完成OFDM处理。 。诸如快速傅立叶变换（FFT）和时间同步之类的OFDM块计算量大，需要并行处理。 OFDM接收器还包含诸如频偏估计之类的任务，这些任务需要处理本质上是串行的泰勒级数和CORDIC算法。串行和并行算法的这种组合可以对HMA的几乎所有设计特征进行全面的探索和评估。 OFDM的实现已导致将CGRA缩放到不同的维度，将处理元素（PE）实例化为多种算术资源，并建立了几乎所有可能的PE互连方式。它进一步探索了用于CGRA存储器中数据放置的时分复用模式。但是，通过使用直接内存访问设备，数据也可以同时通过NoC结构在不同节点之间进行交换。在这项实验性工作中，每个CGRA的性能，整个平台的总体性能以及NoC流量都根据时钟周期数和几个高级性能指标进行记录。对于他们设计的应用程序而言，当今的HMA通常资源过多或不足，因此对于最终用户而言并不是最佳选择。除了与其他最新技术进行有趣的比较之外，我们的实验设置还提供了重要的见识和指导原则，设计人员可以使用它们来为目标应用实现接近最佳的解决方案。

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