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A Survey Of Techniques for Architecting DRAM Caches

机译：构造DRAM缓存的技术概述

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摘要

Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture. In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. Efficient integration of DRAM caches in mainstream computing systems, however, also presents several challenges and several recent techniques have been proposed to address them. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.
机译：内核数和内存/带宽墙增加的最新趋势导致了芯片架构的重大改革。面对日益增长的缓存容量需求，研究人员现在探索了DRAM（通常被认为是主内存的代名词），以设计大型的末级缓存。然而，主流计算系统中DRAM高速缓存的有效集成也带来了一些挑战，并且已经提出了一些最新技术来解决这些挑战。在本文中，我们对构成DRAM缓存的技术进行了概述。此外，通过对这些技术进行几个方面的分类，我们强调了它们的相似之处和不同之处。我们认为，这篇论文对于研究人员了解DRAM缓存的潜力，权衡和挑战很有帮助。

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