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Cache-Hierarchy Contention-Aware Scheduling in CMPs

机译：CMP中的缓存层次结构竞争感知调度

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To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, contention points may appear along the whole memory hierarchy. Moreover, this problem is expected to aggravate in future technologies, since the number of cores and hardware threads, and consequently the size of the shared caches increase with each microprocessor generation. This paper characterizes the impact on performance of the different contention points that appear along the memory subsystem. The analysis shows that some benchmarks are more sensitive to contention in higher levels of the memory hierarchy (e.g., shared L2) than to main memory contention. In this paper, we propose two generic scheduling strategies for CMPs. The first strategy takes into account the available bandwidth at each level of the cache hierarchy. The strategy selects the processes to be coscheduled and allocates them to cores to minimize contention effects. The second strategy also considers the performance degradation each process suffers due to contention-aware scheduling. Both proposals have been implemented and evaluated in a commercial single-threaded quad-core processor with a relatively small two-level cache hierarchy. The proposals reach, on average, a performance improvement by 5.38 and 6.64 percent when compared with the Linux scheduler, while this improvement is by 3.61 percent for an state-of-the-art memory contention-aware scheduler under the evaluated mixes.
机译：为了提高芯片多处理器（CMP）的性能，最近的研究集中在调度策略上，以减轻主存储器带宽争用。如今，商业CMP实现了由多个多线程内核共享的多级缓存层次结构。在这种微处理器设计中，争用点可能会出现在整个内存层次结构中。此外，由于内核和硬件线程的数量以及因此共享缓存的大小随着每一代微处理器的增加而增加，预计该问题将在未来的技术中加剧。本文描述了内存子系统中出现的不同竞争点对性能的影响。分析表明，某些基准测试对更高级别的存储器层次结构（例如，共享的L2）比对主存储器竞争更敏感。在本文中，我们提出了CMP的两种通用调度策略。第一种策略考虑了缓存层次结构每个级别上的可用带宽。该策略选择要共同调度的流程，并将其分配给核心以最大程度地减少竞争影响。第二种策略还考虑了每个进程由于感知竞争的调度而导致的性能下降。两种建议均已在具有相对较小的二级缓存层次结构的商用单线程四核处理器中实现和评估。与Linux调度程序相比，这些建议的性能平均提高了5.38％和6.64％，而在评估的混合环境下，最先进的内存争用感知调度程序的性能提高了3.61％。

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