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首页> 外文期刊>Parallel and Distributed Systems, IEEE Transactions on >Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)
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Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)

机译：流水线多处理器片上系统（MPSoC）的性能评估

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摘要

The paradigm of pipelined MPSoC (processors connected in a pipeline) is well suited to data flow nature of multimedia applications. Often design space exploration is performed to optimize execution time, latency or throughput of a pipelined MPSoC where the variants in the system are processor configurations due to customizable options in each of the processors. Since there can be billions of combinations of processor configurations (design points), the challenge is to quickly provide estimates of performance metrics of those design points. Hence, in this article, we propose analytical models to estimate execution time, latency and throughput of a pipelined MPSoC's design points, avoiding slow full-system cycle accurate simulations of all the design points. For effective use of these analytical models, latencies of individual processor configurations should be available. We propose two estimation methods (PS and PSP) to quickly gather latencies of processor configurations with reduced number of simulations. The PS method simulates all the processor configurations once, while the PSP method simulates only a subset of processor configurations and then uses a processor analytical model to estimate the latencies of the remaining processor configurations. We experimented with several pipelined MPSoCs executing typical multimedia applications (JPEG encoder/decoder, MP3 encoder and H.264 encoder). Our results show that the analytical models with PS and PSP methods had maximum absolute error of 12.95 percent and 18.67 percent respectively, and minimum fidelity of 0.93 and 0.88 respectively. The design spaces of the pipelined MPSoCs ranged from $10^{12}$ to $10^{18}$ design points, and hence simulation of all design points will take years and is infeasible. Compared to PS method, the PSP method reduced simulation time from days to several hour- .
机译：流水线式MPSoC（连接在流水线中的处理器）的范例非常适合多媒体应用程序的数据流性质。通常执行设计空间探索来优化流水线MPSoC的执行时间，等待时间或吞吐量，其中由于每个处理器中的可定制选项，系统中的变体都是处理器配置。由于可能有数十亿个处理器配置（设计点）组合，因此面临的挑战是快速提供这些设计点的性能指标估计。因此，在本文中，我们提出了分析模型来估计流水线MPSoC设计点的执行时间，等待时间和吞吐量，从而避免了所有设计点的缓慢的全系统周期精确仿真。为了有效地使用这些分析模型，应提供各个处理器配置的延迟。我们提出了两种估计方法（PS和PSP），以减少仿真次数来快速收集处理器配置的延迟。 PS方法一次模拟所有处理器配置，而PSP方法仅模拟处理器配置的一个子集，然后使用处理器分析模型来估计其余处理器配置的等待时间。我们对几种执行典型多媒体应用（JPEG编码器/解码器，MP3编码器和H.264编码器）的流水线MPSoC进行了实验。我们的结果表明，采用PS和PSP方法的分析模型的最大绝对误差分别为12.95％和18.67％，最小保真度分别为0.93和0.88。流水线式MPSoC的设计空间从 $ 10 ^ {12} $ 到 $ 10 ^ {18} $ 设计点，因此对所有设计点进行仿真将花费数年且不可行。与PS方法相比，PSP方法将模拟时间从几天减少到几个小时。

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