• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations
【24h】

Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations

机译：扩展神经网络硬件实现的可扩展分层片上网络体系结构

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.
机译：尖峰神经网络（SNN）试图基于大规模并行排列的神经元阵列（通过尖峰事件进行通信）来模拟哺乳动物大脑中的信息处理。与传统的冯·诺依曼计算机范例相比，SNN提供了实现嵌入的神经形态电路的可能性，该电路具有高并行度和低功耗。然而，传统的基于共享总线拓扑的神经元互连实现所表现出的模块化和连接性差的现状，阻碍了SNN的可扩展硬件实现。本文提出了一种用于SNN硬件的新型分层芯片网络（H-NoC）架构，旨在通过使用低级和高级路由器的分层结构创建神经元簇的模块化阵列来解决可伸缩性问题。提出的H-NoC体系结构结合了峰值流量压缩技术，以利用SNN流量模式和神经元之间的位置，从而减少流量开销并提高网络吞吐量。此外，群集之间的自适应路由功能可以平衡本地和全局流量负载，以在突发活动下维持吞吐量。分析结果显示了所提出的H-NoC方法在不同情况下的可扩展性，而使用65纳米CMOS技术进行的仿真和综合分析则分别显示了每个集群的高吞吐量，低成本区域和功耗。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号