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Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters

机译：快速并行循环仲裁器的算法-硬件协同设计

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摘要

As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, which is specially designed for hardware implementation. We prove that our PRRA achieves round-robin fairness under all input patterns. We further propose an improved (IPRRA) design that reduces the timing of PRRA significantly. Simulation results with TSMC .18mum standard cell library show that PRRA and IPRRA can meet the timing requirement of a terabit 256 times 256 switch. Both PRRA and IPRRA are much faster and simpler than the programmable priority encoder (PPE), a well-known round-robin arbiter design. We also introduce an additional design which combines PRRA and IPRRA and provides trade-offs in gate delay, wire delay, and circuit area. With the binary tree structure and high performance, our designs are scalable for large N and useful for implementing schedulers for high-speed switches and routers
机译：作为交换调度程序的基本组成部分，快速而公平的仲裁器对于调度程序的效率至关重要，而这对于高速交换器或路由器的性能至关重要。在本文中，我们提出了一种基于简单二进制搜索算法的并行循环仲裁器（PRRA），该算法是专门为硬件实现而设计的。我们证明我们的PRRA在所有输入模式下均实现了轮询公平性。我们进一步提出了一种改进的（IPRRA）设计，该设计可显着减少PRRA的时间。台积电.18mum标准单元库的仿真结果表明，PRRA和IPRRA可以满足256 TB 256 TB的时序要求。 PRRA和IPRRA都比可编程优先级编码器（PPE）（一种众所周知的循环仲裁器设计）更快，更简单。我们还介绍了结合了PRRA和IPRRA的另一种设计，并在栅极延迟，布线延迟和电路面积方面进行了权衡。凭借二叉树结构和高性能，我们的设计可扩展用于大N，并有助于实现高速交换机和路由器的调度程序

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